Altera Arria V GT FPGA Development Board - Manual (Page 75)

Chapter 2: Board Components 2–65
Memory
December 2014 Altera Corporation Arria V GT FPGA Development Board
Reference Manual
N11 QDRII_D1 AB27 1.8-V HSTL Write data bus
M11 QDRII_D2 AB28 1.8-V HSTL Write data bus
K10 QDRII_D3 AM28 1.8-V HSTL Write data bus
J11 QDRII_D4 AC27 1.8-V HSTL Write data bus
G11 QDRII_D5 AD27 1.8-V HSTL Write data bus
E10 QDRII_D6 AR28 1.8-V HSTL Write data bus
D11 QDRII_D7 AU28 1.8-V HSTL Write data bus
C11 QDRII_D8 AV28 1.8-V HSTL Write data bus
N10 QDRII_D9 AW29 1.8-V HSTL Write data bus
M9 QDRII_D10 AW28 1.8-V HSTL Write data bus
L9 QDRII_D11 AR27 1.8-V HSTL Write data bus
J9 QDRII_D12 AT27 1.8-V HSTL Write data bus
G10 QDRII_D13 AU27 1.8-V HSTL Write data bus
F9 QDRII_D14 AN27 1.8-V HSTL Write data bus
D10 QDRII_D15 AV27 1.8-V HSTL Write data bus
C9 QDRII_D16 AW27 1.8-V HSTL Write data bus
B9 QDRII_D17 AH27 1.8-V HSTL Write data bus
B3 QDRII_D18 AC25 1.8-V HSTL Write data bus
C3 QDRII_D19 AF27 1.8-V HSTL Write data bus
D2 QDRII_D20 AD25 1.8-V HSTL Write data bus
F3 QDRII_D21 AG26 1.8-V HSTL Write data bus
G2 QDRII_D22 AH26 1.8-V HSTL Write data bus
J3 QDRII_D23 AE26 1.8-V HSTL Write data bus
L3 QDRII_D24 AG25 1.8-V HSTL Write data bus
M3 QDRII_D25 AH25 1.8-V HSTL Write data bus
N2 QDRII_D26 AP26 1.8-V HSTL Write data bus
C1 QDRII_D27 AN25 1.8-V HSTL Write data bus
D1 QDRII_D28 AK25 1.8-V HSTL Write data bus
E2 QDRII_D29 AT26 1.8-V HSTL Write data bus
G1 QDRII_D30 AU26 1.8-V HSTL Write data bus
J1 QDRII_D31 AT25 1.8-V HSTL Write data bus
K2 QDRII_D32 AW25 1.8-V HSTL Write data bus
M1 QDRII_D33 AW26 1.8-V HSTL Write data bus
N1 QDRII_D34 AL26 1.8-V HSTL Write data bus
P2 QDRII_D35 AV25 1.8-V HSTL Write data bus
H1 QDRII_DOFFN AN24 1.8-V HSTL DLL enable
A6 QDRII_K_N AE25 1.8-V HSTL Write clock N
B6 QDRII_K_P AF25 1.8-V HSTL Write clock P
P11 QDRII_Q0 AD24 1.8-V HSTL Read data bus
Table 2–34. QDRII+ Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3)
Board
Reference (U8)
Schematic
Signal Name
Arria V GT FPGA
Pin Number
I/O Standard Description