Altera Arria V GT FPGA Development Board - Manual (Page 37)

Chapter 2: Board Components 2–27
General User Input/Output
December 2014 Altera Corporation Arria V GT FPGA Development Board
Reference Manual
General User Input/Output
This section describes the user I/O interface to the FPGA, including the push buttons,
DIP switches, status LEDs, character LCD, and SDI video output/input port.
User-Defined Push Buttons
The development board includes three user-defined push buttons for each FPGA
device. For information on the system and safe reset push buttons, refer to
“Setup
Elements” on page 2–20 .
Board references S5, S6, and S7 are push buttons that allow you to interact with the
Arria V GT FPGA 1 while S9, S10, and S11 are for use with the Arria V GT FPGA 2.
When you press and hold down the button, the device pin is set to logic 0; when you
release the button, the device pin is set to logic 1. There are no board-specific functions
for these general user push buttons.
Table 2–14 lists the user-defined push button schematic signal names and their
corresponding Arria V GT FPGA device pin numbers.
User-Defined DIP Switches
Board references SW2 and SW3 are two sets of eight-pin DIP switches. There are no
board-specific functions for these switches. Each of the Arria V GT FPGA have a set of
user-defined DIP switch. When the switch is in the OFF position, a logic 1 is selected.
When the switch is in the ON position, a logic 0 is selected.
Table 2–14. User-Defined Push Button Schematic Signal Names and Functions
Board Reference
Schematic Signal
Name
Arria V GT FPGA Pin
Number
I/O Standard Description
S6 USER1_PB0 U16.T19 2.5-V
User-defined push buttons for
FPGA 1.
S5 USER1_PB1 U16.R19 2.5-V
S4 USER1_PB2 U16.F18 2.5-V
S11 USER2_PB0 U13.D6 2.5-V
User-defined push buttons for
FPGA 2.
S10 USER2_PB1 U13.C6 2.5-V
S9 USER2_PB2 U13.K7 2.5-V