Altera Arria V GT FPGA Development Board - Manual (Page 18)

2–8 Chapter 2: Board Components
MAX II CPLD EPM2210 System Controller
Arria V GT FPGA Development Board December 2014 Altera Corporation
Reference Manual
MAX II CPLD EPM2210 System Controller
The board utilizes the EPM2210 System Controller, an Altera MAX II CPLD, for the
following purposes:
■ FPGA configuration from flash
■ Power consumption monitoring
■ Virtual JTAG interface for PC-based GUI
■ Control registers for clocks
■ Control registers for remote system update
Figure 2–3 illustrates the MAX II CPLD EPM2210 System Controller's functionality
and external circuit connections as a block diagram.
Clocks or Oscillators 1.8-V CMOS + LVDS 10 5 differential clocks, 1 single-ended
Total I/O Used: 584
Transceivers
SMAs or Bull's Eye — 12 —
HSMC port B — 16 —
FMC — 40 —
Chip-to-chip bridge — 32 —
Total Transceivers: 116
Table 2–4. Arria V GT FPGA 2 Pin Count and Usage (Part 2 of 2)
Function I/O Standard I/O Count Special Pins
Figure 2–3. MAX II CPLD EPM2210 System Controller Block Diagram
Information
Register
Embedded
Blaster
MAX II CPLD
Power
Calculations
SLD-HUB
PFL
Power
Measurement
Results
Virtual-JTAG
PC
Arria V
FPGA
LTC2418
Controller
Flash
Decoder Encoder
GPIO
JTAG Control
Control
Register