Altera Arria V GT FPGA Development Board - Manual (Page 73)

Chapter 2: Board Components 2–63
Memory
December 2014 Altera Corporation Arria V GT FPGA Development Board
Reference Manual
L8 DDR3B_ZQ4 — 1.5-V SSTL Class I ZQ impedance calibration
DDR3C (U22)
E7 DDR3C_DM2 J23 1.5-V SSTL Class I Write mask byte lane
D3 DDR3C_DM3 D25 1.5-V SSTL Class I Write mask byte lane
E3 DDR3C_DQ16 C24 1.5-V SSTL Class I Data bus byte lane
F7 DDR3C_DQ17 M23 1.5-V SSTL Class I Data bus byte lane
F2 DDR3C_DQ18 B24 1.5-V SSTL Class I Data bus byte lane
F8 DDR3C_DQ19 R23 1.5-V SSTL Class I Data bus byte lane
H3 DDR3C_DQ20 G24 1.5-V SSTL Class I Data bus byte lane
H8 DDR3C_DQ21 G23 1.5-V SSTL Class I Data bus byte lane
G2 DDR3C_DQ22 F24 1.5-V SSTL Class I Data bus byte lane
H7 DDR3C_DQ23 F23 1.5-V SSTL Class I Data bus byte lane
D7 DDR3C_DQ24 R24 1.5-V SSTL Class I Data bus byte lane
C3 DDR3C_DQ25 G25 1.5-V SSTL Class I Data bus byte lane
C8 DDR3C_DQ26 T26 1.5-V SSTL Class I Data bus byte lane
C2 DDR3C_DQ27 E25 1.5-V SSTL Class I Data bus byte lane
A7 DDR3C_DQ28 N24 1.5-V SSTL Class I Data bus byte lane
A2 DDR3C_DQ29 K24 1.5-V SSTL Class I Data bus byte lane
B8 DDR3C_DQ30 T25 1.5-V SSTL Class I Data bus byte lane
A3 DDR3C_DQ31 P24 1.5-V SSTL Class I Data bus byte lane
G3 DDR3C_DQS_N2 E24 1.5-V SSTL Class I Data strobe N byte lane
B7 DDR3C_DQS_N3 B25 1.5-V SSTL Class I Data strobe N byte lane
F3 DDR3C_DQS_P2 D24 1.5-V SSTL Class I Data strobe P byte lane
C7 DDR3C_DQS_P3 A25 1.5-V SSTL Class I Data strobe P byte lane
L8 DDR3B_ZQ3 — 1.5-V SSTL Class I ZQ impedance calibration
Table 2–33. DDR3 x64 Devices Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3)
Board Reference
Schematic
Signal Name
Arria V GT FPGA
Pin Number
I/O Standard Description