Altera Arria V GT FPGA Development Board - Manual (Page 45)

Chapter 2: Board Components 2–35
Components and Interfaces
December 2014 Altera Corporation Arria V GT FPGA Development Board
Reference Manual
B20 PCIE_RX_N1 AT38 1.4-V PCML Receive bus
B24 PCIE_RX_N2 AP38 1.4-V PCML Receive bus
B28 PCIE_RX_N3 AM38 1.4-V PCML Receive bus
B34 PCIE_RX_N4 AH38 1.4-V PCML Receive bus
B38 PCIE_RX_N5 AF38 1.4-V PCML Receive bus
B42 PCIE_RX_N6 AD38 1.4-V PCML Receive bus
B46 PCIE_RX_N7 AB38 1.4-V PCML Receive bus
B14 PCIE_RX_P0 AW37 1.4-V PCML Receive bus
B19 PCIE_RX_P1 AT39 1.4-V PCML Receive bus
B23 PCIE_RX_P2 AP39 1.4-V PCML Receive bus
B27 PCIE_RX_P3 AM39 1.4-V PCML Receive bus
B33 PCIE_RX_P4 AH39 1.4-V PCML Receive bus
B37 PCIE_RX_P5 AF39 1.4-V PCML Receive bus
B41 PCIE_RX_P6 AD39 1.4-V PCML Receive bus
B45 PCIE_RX_P7 AB39 1.4-V PCML Receive bus
B5 PCIE_SMBCLK AV18 1.4-V PCML SMB clock
B6 PCIE_SMBDAT AM16 1.4-V PCML SMB data
A17 PCIE_TX_CN0 AU36 1.4-V PCML Transmit bus
A22 PCIE_TX_CN1 AR36 1.4-V PCML Transmit bus
A26 PCIE_TX_CN2 AN36 1.4-V PCML Transmit bus
A30 PCIE_TX_CN3 AL36 1.4-V PCML Transmit bus
A36 PCIE_TX_CN4 AG36 1.4-V PCML Transmit bus
A40 PCIE_TX_CN5 AE36 1.4-V PCML Transmit bus
A44 PCIE_TX_CN6 AC36 1.4-V PCML Transmit bus
A48 PCIE_TX_CN7 AA36 1.4-V PCML Transmit bus
A16 PCIE_TX_CP0 AU37 1.4-V PCML Transmit bus
A21 PCIE_TX_CP1 AR37 1.4-V PCML Transmit bus
A25 PCIE_TX_CP2 AN37 1.4-V PCML Transmit bus
A29 PCIE_TX_CP3 AL37 1.4-V PCML Transmit bus
A35 PCIE_TX_CP4 AG37 1.4-V PCML Transmit bus
A39 PCIE_TX_CP5 AE37 1.4-V PCML Transmit bus
A43 PCIE_TX_CP6 AC37 1.4-V PCML Transmit bus
A47 PCIE_TX_CP7 AA37 1.4-V PCML Transmit bus
B11 PCIE_WAKEN_R AL16 1.4-V PCML Wake signal
Table 2–24. PCI Express Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (J4)
Schematic Signal Name
Arria V GT FPGA
Pin Number
I/O Standard Description