Altera Arria V GT FPGA Development Board User Manual
Page 23
Chapter 2: Board Components
2–13
MAX II CPLD EPM2210 System Controller
December 2014
Altera Corporation
Arria V GT FPGA Development Board
Reference Manual
PGM1_LED0
A4
2.5-V
Flash memory PGM select indicator 0
PGM1_LED1
F7
2.5-V
Flash memory PGM select indicator 1
PGM1_LED2
C5
2.5-V
Flash memory PGM select indicator 2
PGM1_SEL
D6
2.5-V
Toggles the PGM_LED[0:2] LED sequence
PHASE0
P8
2.5-V
LTM4601 phase control
SDI_A_RX_BYPASS
A8
2.5-V
SDI equalization bypass
SDI_A_RX_EN
E9
2.5-V
SDI receive enable
SDI_A_TX_EN
F9
2.5-V
SDI transmit enable
SENSE_CS0N
F12
2.5-V
Power monitor chip select
SENSE_CS1N
B15
2.5-V
Power monitor chip select
SENSE_SCK
E12
2.5-V
Power monitor SPI clock
SENSE_SDI
A15
2.5-V
Power monitor SPI data in
SENSE_SDO
D12
2.5-V
Power monitor SPI data out
SI570_EN
A13
2.5-V
Si570 programmable oscillator enable
SI571_EN
C13
2.5-V
Si571 programmable VCXO enable
USB_CFG0
H14
1.8-V
On-board USB-Blaster II data
USB_CFG1
H13
1.8-V
On-board USB-Blaster II data
USB_CFG2
G13
1.8-V
On-board USB-Blaster II data
USB_CFG3
F17
1.8-V
On-board USB-Blaster II data
USB_CFG4
G12
1.8-V
On-board USB-Blaster II data
USB_CFG5
F18
1.8-V
On-board USB-Blaster II data
USB_CFG6
H16
1.8-V
On-board USB-Blaster II data
USB_CFG7
G16
1.8-V
On-board USB-Blaster II data
USB_CFG8
H15
1.8-V
On-board USB-Blaster II data
USB_CFG9
G17
1.8-V
On-board USB-Blaster II data
USB_CFG10
G14
1.8-V
On-board USB-Blaster II data
USB_CFG11
G18
1.8-V
On-board USB-Blaster II data
USB_CLK
J6
2.5-V
On-board USB-Blaster II clock
VCCINT_SCL
R3
2.5-V
LTC3880 serial clock
VCCINT_SDA
R2
2.5-V
LTC3880 serial data
Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 5 of 5)
Schematic Signal Name
MAX II CPLD
Pin Number
I/O Standard
Description