Altera Arria V GT FPGA Development Board - Manual (Page 31)

Chapter 2: Board Components 2–21
Configuration, Status, and Setup Elements
December 2014 Altera Corporation Arria V GT FPGA Development Board
Reference Manual
PCI Express Control DIP Switch
The PCI Express control DIP switch (SW7) is provided to enable or disable different
configurations.
Table 2–10 lists the switch controls and descriptions.
CPU Reset Push Button
Each Arria V GT FPGA has a CPU reset push button, CPU1_RESETn (S4) for FPGA 1 and
CPU2_RESETn (S8) for FPGA 2. Both these push buttons are inputs to the Arria V GT
FPGA DEV_CLRn pin and are open-drain I/Os from the MAX II CPLD System
Controller. The push button is the default reset for both the FPGA and CPLD logic.
The MAX II System Controller also drives these push button during POR.
1
You must enable the CPU_RESETn signal within the Quartus II software for this reset
function to work. Otherwise, the CPU_RESETn acts as a regular I/O pin. When you
enable the signal in the Quartus II software, and then pull high on the board, every
register within the FPGA resets to a low signal.
MAX II Reset Push Button
The MAX II reset push button, MAX_RESETn , is an input to the MAX II CPLD System
Controller. This push button is the default reset for the CPLD logic.
Configuration Push Button
The configuration push button, PGM1_CONFIG (S3), is an input to the MAX II CPLD
EPM2210 System Controller. The push button forces a reconfiguration of the FPGA
from flash memory. The location in the flash memory is based on the settings of the
PGM1_LED[2:0]
, which is controlled by the image select push button, PGM1_SEL (S2).
Valid settings include PGM1_LED0, PGM1_LED1, or PGM1_LED2 on the three pages in flash
memory reserved for FPGA designs.
3 FMC_JTAG_EN
ON : Bypass FMC connector
OFF : FMC connector in-chain
4 NC Unused
Table 2–10. PCI Express Control DIP Switch Controls
Switch Schematic Signal Name Description
1 PCIE_PRSNT2n_x1
ON : Enable x1 presence detect
OFF : Disable x1 presence detect
2 PCIE_PRSNT2n_x4
ON : Enable x4 presence detect
OFF : Disable x4 presence detect
3 PCIE_PRSNT2n_x8
ON : Enable x8 presence detect
OFF : Disable x8 presence detect
4 NC Unused
Table 2–9. JTAG Chain Header Switch Controls (Part 2 of 2)
Switch Schematic Signal Name Description