Altera Arria V GT FPGA Development Board - Manual (Page 5)

December 2014 Altera Corporation Arria V GT FPGA Development Board
Reference Manual
1. Overview
This document describes the hardware features of the Arria ® V GT FPGA
development board, including the detailed pin-out and component reference
information required to create custom FPGA designs that interface with all
components of the board.
General Description
The Arria V GT FPGA development board provides a hardware platform for
developing and prototyping low-power, high-performance, and logic-intensive
designs using Altera’s Arria V GT FPGA device. The board provides a wide range of
peripherals and memory interfaces to facilitate the development of Arria V GT FPGA
designs.
Two high-speed mezzanine card (HSMC) connectors are available to add additional
functionality via a variety of HSMCs available from Altera
® and various partners.
f To see a list of the latest HSMCs available or to download a copy of the HSMC
specification, refer to the
Development Board Daughtercards page of the Altera
website.
Design advancements and innovations, such as the PCI Express hard IP
implementation and programmable power technology ensure that designs
implemented in the Arria V GT FPGAs operate faster, with lower power, and have a
faster time to market than previous FPGA families.
f For more information on the following topics, refer to the respective documents:
■ Arria V device family, refer to the Arria V Device Handbook .
■ PCI Express MegaCore function, refer to the PCI Express Compiler User Guide .
■ HSMC Specification, refer to the High Speed Mezzanine Card (HSMC) Specification .