Altera Arria V GT FPGA Development Board - Manual (Page 63)

Chapter 2: Board Components 2–53
Components and Interfaces
December 2014 Altera Corporation Arria V GT FPGA Development Board
Reference Manual
Figure 2–11 shows a diagram of the color coded Bull's Eye connections. Follow the
color code to make loopback connections. For example, connect purple to purple
(pins 17 to 21) for RX to TX loopback. The only pins not connected are pins 3 and 4.
1
You can order more cables from www.samtec.com and these cable systems can be
reused on other boards.
f
For specific instructions on how to install the connector to the board and insert the
cables into the connector, refer to
Samtec's web page regarding this system.
Table 2–30 lists the Bull’s eye connector pin assignments, signal names, and functions.
Figure 2–11. Bull’s Eye Connections
Table 2–30. Bull’s Eye Connector Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (J16)
Schematic Signal Name
Arria V GT FPGA
Pin Number
I/O Standard Description
4 BULLSEYE_SMA_CLKN — LVDS or 2.5-V Clock buffer
3 BULLSEYE_SMA_CLKP — LVDS or 2.5-V Clock buffer
21 SMA_A_10G_RX_N0 G2 LVDS or 2.5-V Transceiver channel
2 SMA_A_10G_RX_N1 H38 LVDS or 2.5-V Transceiver channel
22 SMA_A_10G_RX_P0 G1 LVDS or 2.5-V Transceiver channel
1 SMA_A_10G_RX_P1 H39 LVDS or 2.5-V Transceiver channel
7 SMA_A_6G_RX_N2 C2 LVDS or 2.5-V Transceiver channel
11 SMA_A_6G_RX_P2 C1 LVDS or 2.5-V Transceiver channel
13 SMA_A_TX_L15_N G36 LVDS or 2.5-V Transceiver channel
12 SMA_A_TX_L15_P G37 LVDS or 2.5-V Transceiver channel
17 SMA_A_TX_R16_N F4 LVDS or 2.5-V Transceiver channel
18 SMA_A_TX_R16_P F3 LVDS or 2.5-V Transceiver channel
8 SMA_A_TX_R17_N B4 LVDS or 2.5-V Transceiver channel
9 SMA_A_TX_R17_P B3 LVDS or 2.5-V Transceiver channel
15 SMA_B_10G_RX_N1 H38 LVDS or 2.5-V Transceiver channel