Altera Arria V GT FPGA Development Board - Manual (Page 34)

2–24 Chapter 2: Board Components
Clock Circuitry
Arria V GT FPGA Development Board December 2014 Altera Corporation
Reference Manual
Table 2–11 lists the oscillators, its I/O standard, and voltages required for the
development board.
Table 2–11. On-Board Oscillators
Source
Schematic Signal
Name
Frequency I/O Standard
Arria V GT
FPGA Pin
Number
Application
X6 to U51 1:3
clock buffer
CLKIN_MAX_50
50.000 MHz
1.8-V —
Nios II and MAX II CPLD CLKINA_50 1.8-V AF21
CLKINB_50 1.8-V AP34
X3 CLK_CONFIG 100.000 MHz 2.5-V CMOS — Fast FPGA configuration
X7 to U56 1:6
clock buffer
REFCLK1_A_QL0_P
100.000 MHz
LVDS
(fanout buffer)
AE31
PCI Express host/dual-XTL
REFCLK1_A_QL0_N AE32
CLKINBOTA_P0 AD20
Bottom edge FPGA 1 – QDRII+
CLKINBOTA_N0 AC21
CLKINTOPA_P0 C20
Top edge FPGA 1 – DDR3
CLKINTOPA_N0 D20
CLKINBOTB_P0 AK7
Bottom edge FPGA 2
CLKINBOTB_N0 AJ7
CLKINTOPB_P0 C34
Top edge FPGA 2 – DDR3
CLKINTOPB_N0 D34
X1
CLKA_125_P
125.000 MHz
LVDS AP34 Fixed clock at 125 MHz for
FPGA 1 bank 3A
CLKA_125_N LVDS AN34
X4
CLKB_125_P
125.000 MHz
LVDS AD20 Fixed clock at 125 MHz for
FPGA 1 bank 3D
CLKB_125_N LVDS AC21
X2
REFCLK0_QR0_P
148.500 MHz
LVDS —
HD-SDI video
REFCLK0_QL2_N LVDS —
U53
REFCLK4_A_QL2_P
625.000 MHz
LVDS W31
SFP+
REFCLK4_A_QL2_N LVDS W32
REFCLK3_A_BUF_P
156.250 MHz
LVDS —
SFP+, Bull's Eye connector,
1:2 clock to REFCLK3 on FPGA 1,
REFCLK3_A_BUF_N LVDS —
REFCLK2_A_QL1_P
125.000 MHz
LVDS U31
REFCLK2_A_QL1_N LVDS U32
CLKINBOTA_P1
125.000 MHz
LVDS AL20
Bottom edge FPGA 1 – memory
CLKINBOTA_N1 LVDS AK20
U48
REFCLK4_A_QR2_P
125.000 MHz
LVDS T9
HSMC port A, C2C
REFCLK4_A_QR2_N LVDS T8
REFCLK2_A_QR1_P
100.000 MHz
LVDS AB9
REFCLK2_A_QR1_N LVDS AB8
REFCLK0_A_QR0_P
625.000 MHz
LVDS AF8
C2C
REFCLK0_A_QR0_N LVDS AF7
CLKINTOPA_P1
125.000 MHz
LVDS A22
Top edge FPGA 1 – memory
CLKINTOPA_N1 LVDS A21