Altera Arria V GT FPGA Development Board - Manual (Page 67)

Chapter 2: Board Components 2–57
Memory
December 2014 Altera Corporation Arria V GT FPGA Development Board
Reference Manual
H8 DDR3A_DQ53 N24 1.5-V SSTL Class I Data bus byte lane
G2 DDR3A_DQ54 G25 1.5-V SSTL Class I Data bus byte lane
H7 DDR3A_DQ55 K24 1.5-V SSTL Class I Data bus byte lane
D7 DDR3A_DQ56 F23 1.5-V SSTL Class I Data bus byte lane
C3 DDR3A_DQ57 J23 1.5-V SSTL Class I Data bus byte lane
C8 DDR3A_DQ58 G23 1.5-V SSTL Class I Data bus byte lane
C2 DDR3A_DQ59 C24 1.5-V SSTL Class I Data bus byte lane
A7 DDR3A_DQ60 F24 1.5-V SSTL Class I Data bus byte lane
A2 DDR3A_DQ61 R23 1.5-V SSTL Class I Data bus byte lane
B8 DDR3A_DQ62 G24 1.5-V SSTL Class I Data bus byte lane
A3 DDR3A_DQ63 M23 1.5-V SSTL Class I Data bus byte lane
G3 DDR3A_DQS_N6 B25 1.5-V SSTL Class I Data strobe N byte lane
B7 DDR3A_DQS_N7 E24 1.5-V SSTL Class I Data strobe N byte lane
F3 DDR3A_DQS_P6 A25 1.5-V SSTL Class I Data strobe P byte lane
C7 DDR3A_DQS_P7 D24 1.5-V SSTL Class I Data strobe P byte lane
L8 DDR3A_ZQ04 — 1.5-V SSTL Class I ZQ impedance calibration
DDR3A (U18)
E7 DDR3A_DM4 E27 1.5-V SSTL Class I Write mask byte lane
D3 DDR3A_DM5 A26 1.5-V SSTL Class I Write mask byte lane
E3 DDR3A_DQ32 P27 1.5-V SSTL Class I Data bus byte lane
F7 DDR3A_DQ33 B27 1.5-V SSTL Class I Data bus byte lane
F2 DDR3A_DQ34 R27 1.5-V SSTL Class I Data bus byte lane
F8 DDR3A_DQ35 C27 1.5-V SSTL Class I Data bus byte lane
H3 DDR3A_DQ36 M27 1.5-V SSTL Class I Data bus byte lane
H8 DDR3A_DQ37 H27 1.5-V SSTL Class I Data bus byte lane
G2 DDR3A_DQ38 N27 1.5-V SSTL Class I Data bus byte lane
H7 DDR3A_DQ39 K27 1.5-V SSTL Class I Data bus byte lane
D7 DDR3A_DQ40 J26 1.5-V SSTL Class I Data bus byte lane
C3 DDR3A_DQ41 D26 1.5-V SSTL Class I Data bus byte lane
C8 DDR3A_DQ42 K25 1.5-V SSTL Class I Data bus byte lane
C2 DDR3A_DQ43 G26 1.5-V SSTL Class I Data bus byte lane
A7 DDR3A_DQ44 T27 1.5-V SSTL Class I Data bus byte lane
A2 DDR3A_DQ45 F26 1.5-V SSTL Class I Data bus byte lane
B8 DDR3A_DQ46 R26 1.5-V SSTL Class I Data bus byte lane
A3 DDR3A_DQ47 C26 1.5-V SSTL Class I Data bus byte lane
G3 DDR3A_DQS_N4 T28 1.5-V SSTL Class I Data strobe N byte lane
B7 DDR3A_DQS_N5 N26 1.5-V SSTL Class I Data strobe N byte lane
F3 DDR3A_DQS_P4 R28 1.5-V SSTL Class I Data strobe P byte lane
C7 DDR3A_DQS_P5 M26 1.5-V SSTL Class I Data strobe P byte lane
Table 2–31. DDR3A Devices Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5)
Board Reference
Schematic
Signal Name
Arria V GT FPGA
Pin Number
I/O Standard Description