Altera Arria V GT FPGA Development Board - Manual (Page 44)

2–34 Chapter 2: Board Components
Components and Interfaces
Arria V GT FPGA Development Board December 2014 Altera Corporation
Reference Manual
The power for the board can be sourced entirely from the PCI Express edge connector
when installed into a PC motherboard. Although the board can also be powered by a
laptop power supply for use on a lab bench, Altera recommends that you do not
power up from both supplies at the same time. Ideal diode power sharing devices
have been designed into this board to prevent damages or back-current from one
supply to the other.
The PCIE_REFCLK_P signal is a 100 MHz differential input that is driven from the PC
motherboard on to this board through the edge connector. This signal connects
directly to a Arria V GT FPGA REFCLK input pin pair using DC coupling. This clock is
terminated on the motherboard and therefore, no on-board termination is required.
This clock can have spread-spectrum properties that change its period between
9.847 ps to 10.203 ps. The I/O standard is High-Speed Current Steering Logic (HCSL).
Figure 2–8 shows the PCI Express reference clock levels.
The JTAG and SMB are optional signals in the PCI Express specification. Therefore,
the JTAG signal loopback from PCI Express TDI to PCI Express TDO and are not used
on this board. The SMB signals are wired to the Arria V GT FPGA but are not required
for normal operation.
Table 2–24 summarizes the PCI Express pin assignments. The signal names and
directions are relative to the Arria V GT FPGA.
Figure 2–8. PCI Express Reference Clock Levels
V MAX = 1.15 V
V CROSS MAX = 550 mV
V CROSS MIN = 250 mV
V MIN = –0.30 V
REFCLK –
REFCLK +
Table 2–24. PCI Express Pin Assignments, Schematic Signal Names, and Functions
Board
Reference (J4)
Schematic Signal Name
Arria V GT FPGA
Pin Number
I/O Standard Description
A5 PCIE_JTAG_TCK — 1.4-V PCML JTAG chain clock
A6 PCIE_JTAG_TDI — 1.4-V PCML JTAG chain data in
A7 PCIE_JTAG_TDO — 1.4-V PCML JTAG chain data out
A8 PCIE_JTAG_TMS — 1.4-V PCML JTAG chain mode select
A11 PCIE_PERSTN N9 1.4-V PCML Presence detect DIP switch
A1 PCIE_PRSNT1N — 1.4-V PCML Presence detect DIP switch
B17 PCIE_PRSNT2N_X1 — 1.4-V PCML Presence detect DIP switch
B31 PCIE_PRSNT2N_X4 — 1.4-V PCML Presence detect DIP switch
B48 PCIE_PRSNT2N_X8 — 1.4-V PCML Presence detect DIP switch
A14 PCIE_REFCLK_N AG33 1.4-V PCML Motherboard reference clock
A13 PCIE_REFCLK_P AG32 1.4-V PCML Motherboard reference clock
B15 PCIE_RX_N0 AW36 1.4-V PCML Receive bus