Altera Arria V GT FPGA Development Board - Manual (Page 17)

Chapter 2: Board Components 2–7
Featured Device: Arria V GT FPGA
December 2014 Altera Corporation Arria V GT FPGA Development Board
Reference Manual
Table 2–3 lists the Arria V GT FPGA 1 pin count and usage by function on the
development board. Clocks are listed under special pins as it uses dedicated I/O pins.
Table 2–4 lists the Arria V GT FPGA 2 pin count and usage by function on the
development board. Clocks are listed under special pins as it uses dedicated I/O pins.
Table 2–3. Arria V GT FPGA 1 Pin Count and Usage
Function I/O Standard I/O Count Special Pins
DDR3 ×72 interface 1.5-V SSTL 125 1 differential ×9 differential DQS
QDRII+ ×36 interface 1.8-V HSTL 103 1 differential ×36 differential DQS
MAX II System Controller 1.8-V CMOS 8 —
Flash 1.8-V CMOS 49 —
PCI Express 2.5-V CMOS 10 1 reference clock
HSMC port A 2.5-V CMOS + LVDS 84 1 reference clock
Gigabit Ethernet 2.5-V CMOS + LVDS 16 —
On-Board USB-Blaster II 1.5-V/2.5-V CMOS 19 —
SFP+ 2.5-V CMOS 16 2 reference clocks
Chip-to-chip bridge 2.5-V 120 2 reference clocks
Buttons 2.5-V CMOS 3 —
Switches 2.5-V CMOS 4 —
LCD 2.5-V CMOS 11 —
LEDs 2.5-V CMOS 16 —
Clocks or Oscillators 1.8-V CMOS + LVDS 10 5 differential clocks, 1 single-ended
Total I/O Used: 625
Transceivers
SMA or Bull’s Eye — 16 —
HSMC port A — 32 —
PCI Express — 32 —
Chip-to-chip bridge — 32 —
SFP+ — 8 —
Total Transceiver Used: 120
Table 2–4. Arria V GT FPGA 2 Pin Count and Usage (Part 1 of 2)
Function I/O Standard I/O Count Special Pins
DDR3 ×64 device 1.5-V SSTL 156 1 differential ×9 differential DQS
HSMC port B 2.5-V CMOS + LVDS 84 1 reference clock
FMC 2.5-V 178 1 reference clock
SDI 2.5-V CMOS 8 1 reference clock
Chip-to-chip bridge 2.5-V 120 1 reference clock
Buttons 2.5-V CMOS 4 —
Switches 2.5-V CMOS 8 —
LEDs 2.5-V CMOS 16 —