Altera Arria V GT FPGA Development Board - Manual (Page 16)

2–6 Chapter 2: Board Components
Featured Device: Arria V GT FPGA
Arria V GT FPGA Development Board December 2014 Altera Corporation
Reference Manual
Featured Device: Arria V GT FPGA
The Arria V GT FPGA development board features two Arria V GT FPGA
5AGTFD7K3F40I3N device (U13 and U16) in a 1517-pin FBGA package.
f For more information about Arria V device family, refer to the Arria V Device
Handbook .
Table 2–2 describes the features of the Arria V GT FPGA 5AGTFD7K3F40I3N device.
I/O Resources
Figure 2–2 illustrates the bank organization and I/O count for the Arria V GT FPGA
5AGTFD7K3F40I3N device in the 1517-pin FBGA package.
Table 2–2. Arria V GT FPGA Features
ALMs
Equivalent
LEs
M10K RAM
Blocks
Total RAM
Kbits
18-bit × 18-bit
Multipliers
PLLs Transceivers Package Type
190,240 504,000 24,140 27,046 2,312 16 36 1517-pin FBGA
Figure 2–2. Arria V GT FPGA Device I/O Bank Diagrams
Bank 3A 48
Bank 3B 32
Bank 3C 48
Bank 3D 48
Bank 4D 48
Bank 4C 32
Bank 8A
Bank 8B
Bank 8C
Bank 8D
Bank 7D
Bank 7C
48
32
48
48
48
32
Bank 4B 48
Bank 4A 48
Bank 7B
Bank 7A
48
48
GXB_L
XCVRs
GXB_R
XCVRs
PCIe
x8
SMA
(10G)
C2C
x8
SMA
(10G)
A1 AW1
DDR3 x72
1.5 V
USB
2.5 V
Chip-to-Chip
1.8 V
QDRII+
Flash/MAX
ENET
2.5 V
LCD
USER
PCIe
SDI
FMC
HSMA
HSMB
2.5 V
Chip-to-Chip
USER
GXB_R
XCVRs
GXB_L
XCVRs
SFP+
x1
FMC
x6
HSMA
x4
C2C
x8
Bank 8A
Bank 8B
Bank 8C
Bank 8D
Bank 7D
Bank 7C
48
32
48
48
48
32
Bank 7B
Bank 7A
48
48
A1
Bank 3A 48
Bank 3B 32
Bank 3C 48
Bank 3D 48
Bank 4D 48
Bank 4C 32
Bank 4B 48
Bank 4A 48
HSMA
x8
FMC
x4
SMA
(6G)
BP
x4
SDI
x1
BP
x4
SMA
(10G)
SFP+
1.5 V
DDR3 x72
HSMB
x4
2.5 V
SFP+
USER
LCD
SMA
(6G)
2.5 V
2.5 V
SFP+
x1
SMA
(6G)
SMA
(10G)
5AGTFD7K3F40I3N
Device 1
5AGTFD7K3F40I3N
Device 2