Altera Arria V GT FPGA Development Board - Manual (Page 27)

Chapter 2: Board Components 2–17
Configuration, Status, and Setup Elements
December 2014 Altera Corporation Arria V GT FPGA Development Board
Reference Manual
Figure 2–5 shows the PFL configuration.
f
For information on the flash memory map storage, refer to the Arria V GT FPGA
Development Kit User Guide .
There are two pages reserved for the FPGA configuration data. The factory hardware
page—page 0—loads upon power-up when the
Factory1 DIP switch (SW5.3) is set to
'1'. Otherwise, the user hardware page 1 loads. Pressing the PGM1_CONFIG push button
(S3) loads the FPGA with a hardware page based on which PGM1_LED[2:0] LED (D12,
D13, D14) illuminates.
Figure 2–5. PFL Configuration
MAX II CPLD
EPM2210 System Controller
Arria V FPGA
FPGA_DATA [7:0]
FPGA_DCLK
FLASH_A [26:1]
FLASH_D [15:0]
DATA [7:0]
DCLK
INIT_DONE
nSTATUS
nCONFIG
CONF_DONE
CONF_DONE
MSEL0
MSEL1
MSEL2
MSEL3
MSEL4
MSEL[4:0] also
goes to MAX II CPLD
2.5 V
10 k Ω
nCE
CFI
Flash
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_A [26:0]
FLASH_D [15:0]
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_WPn
FLASH_ADVn
FPGA_nCONFIG
FPGA_CONF_DONE
FLASH_RYBSYn
FLASH_RYBSYn
FPGA_nSTATUS
FPGA_INIT_DONE
1.8 V
10 k Ω
10 k Ω
FLASH_ADVn
CONF_DONE_LED
2.5 V
FLASH_CLK
FLASH_CLK
FLASH_RSTn
FLASH_RESETn
PS Port
Flash Interface
56.2 Ω
100 Ω 56.2 Ω
56.2 Ω
50 MHz
100 MHz
2.5 V
2.5 V 2.5 V
MAX_ERROR1
MAX_CONF_DONE1
MAX_LOAD1
FACTORY2
FACTORY1
CLK_ENABLE
CLK_SEL
MAX_RESETn
PGM1_CONFIG
PGM1_SEL
PGM1_LED0
PGM1_LED1
PGM1_LED2
DIP Switch
DIP Switch
1 k Ω