Altera Arria V GT FPGA Development Board - Manual (Page 74)

2–64 Chapter 2: Board Components
Memory
Arria V GT FPGA Development Board December 2014 Altera Corporation
Reference Manual
QDRII+
The development board supports a burst-of-4 QDRII+ SRAM memory device for
very-high-speed, low-latency memory access. The QDRII+ has a x36 interface,
providing device addressing of up to a 36 Mb.
The QDRII+ has separate read and write data ports with DDR signaling at up to
550 MHz. The pinout and footprint is compatible with a burst-of-2 QDRII SSRAM
memory device. The FPGA can support up to 400 MHz QDRII data.
Table 2–34 lists the QDRII+ pin assignments, signal names, and functions.
Table 2–34. QDRII+ Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 3)
Board
Reference (U8)
Schematic
Signal Name
Arria V GT FPGA
Pin Number
I/O Standard Description
R9 QDRII_A0 AB29 1.8-V HSTL Address bus
R8 QDRII_A1 AC29 1.8-V HSTL Address bus
B4 QDRII_A2 AF28 1.8-V HSTL Address bus
B8 QDRII_A3 AG28 1.8-V HSTL Address bus
C5 QDRII_A4 AK29 1.8-V HSTL Address bus
C7 QDRII_A5 AL29 1.8-V HSTL Address bus
N5 QDRII_A6 AH28 1.8-V HSTL Address bus
N6 QDRII_A7 AJ28 1.8-V HSTL Address bus
N7 QDRII_A8 AD28 1.8-V HSTL Address bus
P4 QDRII_A9 AP28 1.8-V HSTL Address bus
P5 QDRII_A10 AJ27 1.8-V HSTL Address bus
P7 QDRII_A11 AP27 1.8-V HSTL Address bus
P8 QDRII_A12 AM27 1.8-V HSTL Address bus
R3 QDRII_A13 AG27 1.8-V HSTL Address bus
R4 QDRII_A14 AE27 1.8-V HSTL Address bus
R5 QDRII_A15 AC24 1.8-V HSTL Address bus
R7 QDRII_A16 AD26 1.8-V HSTL Address bus
A9 QDRII_A17 AN26 1.8-V HSTL Address bus
A3 QDRII_A18 AJ25 1.8-V HSTL Address bus
A10 QDRII_A19 AT32 1.8-V HSTL Address bus
A2 QDRII_A20 AU32 1.8-V HSTL Address bus
B7 QDRII_BWSN0 AK27 1.8-V HSTL Write byte write select 0
A7 QDRII_BWSN1 AB25 1.8-V HSTL Write byte write select 1
A5 QDRII_BWSN2 AM25 1.8-V HSTL Write byte write select 2
B5 QDRII_BWSN3 AV24 1.8-V HSTL Write byte write select 3
R6 QDRII_C_N AG24 1.8-V HSTL Clock N
P6 QDRII_C_P AD23 1.8-V HSTL Clock P
A1 QDRII_CQ_N AR21 1.8-V HSTL Echo clock N
A11 QDRII_CQ_P AT21 1.8-V HSTL Echo clock P
P10 QDRII_D0 AE28 1.8-V HSTL Write data bus