Flash, Flash –48 – Altera Cyclone V GT FPGA Development Board User Manual
Page 56
2–48
Chapter 2: Board Components
Memory
Cyclone V GT FPGA Development Board
September 2014
Altera Corporation
Reference Manual
Flash
The development board supports a 1-GB CFI-compatible synchronous flash device for
non-volatile storage of FPGA configuration data, board information, test application
data, and user code space. This device is part of the shared FM bus that connects the
flash memory and MAX V CPLD 5M2210 System Controller.
This 16-bit data interface can sustain burst read operations at up to 52 MHz for a
throughput of 832 Mbps per device. The write performance is 270 µs for a single word
buffer while the erase time is 800 ms for a 128 K array block.
lists the flash pin assignments, signal names, and functions. The signal
names and types are relative to the Cyclone V GT in terms of I/O setting and
direction.
Table 2–30. Flash Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 2)
Board
Reference (U20)
Schematic Signal Name
Cyclone V GT
Pin Number
I/O Standard
Description
F6
FLASH_ADVN
AB34
2.5-V
Address valid
B4
FLASH_CEN
AA21
2.5-V
Chip enable
E6
FLASH_CLK
AE29
2.5-V
Clock
F8
FLASH_OEN
AG16
2.5-V
Output enable
F7
FLASH_RDYBSYN
AD20
2.5-V
Ready
D4
FLASH_RESETN
AB16
2.5-V
Reset
G8
FLASH_WEN
AM14
2.5-V
Write enable
C6
FLASH_WPN
—
2.5-V
Write protect
A1
FSM_A1
AK33
2.5-V
Address bus
B1
FSM_A2
AC27
2.5-V
Address bus
C1
FSM_A3
AB24
2.5-V
Address bus
D1
FSM_A4
AB23
2.5-V
Address bus
D2
FSM_A5
AC28
2.5-V
Address bus
A2
FSM_A6
Y24
2.5-V
Address bus
C2
FSM_A7
Y25
2.5-V
Address bus
A3
FSM_A8
AF27
2.5-V
Address bus
B3
FSM_A9
AF26
2.5-V
Address bus
C3
FSM_A10
AB28
2.5-V
Address bus
D3
FSM_A11
AE28
2.5-V
Address bus
C4
FSM_A12
AB29
2.5-V
Address bus
A5
FSM_A13
AF28
2.5-V
Address bus
B5
FSM_A14
AH28
2.5-V
Address bus
C5
FSM_A15
AB30
2.5-V
Address bus
D7
FSM_A16
AG29
2.5-V
Address bus
D8
FSM_A17
AA30
2.5-V
Address bus
A7
FSM_A18
AK30
2.5-V
Address bus
B7
FSM_A19
AJ30
2.5-V
Address bus
C7
FSM_A20
AG30
2.5-V
Address bus