Altera Cyclone V GT FPGA Development Board - Manual (Page 37)

Chapter 2: Board Components 2–29
Components and Interfaces
September 2014 Altera Corporation Cyclone V GT FPGA Development Board
Reference Manual
The HSMC interface has programmable bi-directional I/O pins that can be used as
2.5-V LVCMOS, which is 3.3-V LVTTL-compatible. These pins can also be used as
various differential I/O standards including, but not limited to, LVDS, mini-LVDS,
and RSDS with up to 17 full-duplex channels.
1 As noted in the High Speed Mezzanine Card (HSMC) Specification manual, LVDS and
single-ended I/O standards are only guaranteed to function when mixed according to
either the generic single-ended pin-out or generic differential pin-out.
Table 2–22 lists the HSMC interface pin assignments, signal names, and functions.
Table 2–22. HSMC Interface Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 6)
Board
Reference
Schematic Signal Name
Cyclone V GT
Pin Number
I/O Standard Description
HSMC Port A (J1)
17 HSMA_TX_P3 P4 1.5-V PCML Transceiver TX bit 3
18 HSMA_RX_P3 R2 1.5-V PCML Transceiver RX bit 3
19 HSMA_TX_N3 P3 1.5-V PCML Transceiver TX bit 3n
20 HSMA_RX_N3 R1 1.5-V PCML Transceiver RX bit 3n
21 HSMA_TX_P2 T4 1.5-V PCML Transceiver TX bit 2
22 HSMA_RX_P2 U2 1.5-V PCML Transceiver RX bit 2
23 HSMA_TX_N2 T3 1.5-V PCML Transceiver TX bit 2n
24 HSMA_RX_N2 U1 1.5-V PCML Transceiver RX bit 2n
25 HSMA_TX_P1 V4 1.5-V PCML Transceiver TX bit 1
26 HSMA_RX_P1 W2 1.5-V PCML Transceiver RX bit 1
27 HSMA_TX_N1 V3 1.5-V PCML Transceiver TX bit 1n
28 HSMA_RX_N1 W1 1.5-V PCML Transceiver RX bit 1n
29 HSMA_TX_P0 Y4 1.5-V PCML Transceiver TX bit 0
30 HSMA_RX_P0 AA2 1.5-V PCML Transceiver RX bit 0
31 HSMA_TX_N0 Y3 1.5-V PCML Transceiver TX bit 0n
32 HSMA_RX_N0 AA1 1.5-V PCML Transceiver RX bit 0n
33 HSMA_SDA K13 2.5-V CMOS Management serial data
34 HSMA_SCL E12 2.5-V CMOS Management serial clock
35 JTAG_TCK AK5 2.5-V CMOS JTAG clock signal
36 HSMA_JTAG_TMS — 2.5-V CMOS JTAG mode select signal
37 HSMA_JTAG_TDO — 2.5-V CMOS JTAG data output
38 JTAG_FPGA_TDO AF11 2.5-V CMOS JTAG data input
39 HSMA_CLK_OUT0 F10 2.5-V CMOS Dedicated CMOS clock out
40 HSMA_CLK_IN0 G11 2.5-V CMOS Dedicated CMOS clock in
41 HSMA_D0 L12 2.5-V CMOS Dedicated CMOS I/O bit 0
42 HSMA_D1 F11 2.5-V CMOS Dedicated CMOS I/O bit 1
43 HSMA_D2 F12 2.5-V CMOS Dedicated CMOS I/O bit 2
44 HSMA_D3 K12 2.5-V CMOS Dedicated CMOS I/O bit 3
47 HSMA_TX_D_P0 B4 LVDS or 2.5-V LVDS TX bit 0 or CMOS bit 4