Altera Cyclone V GT FPGA Development Board - Manual (Page 17)

Chapter 2: Board Components 2–9
MAX V CPLD 5M2210 System Controller
September 2014 Altera Corporation Cyclone V GT FPGA Development Board
Reference Manual
L16 FM_D6 1.8-V FM data bus
L11 FM_D7 1.8-V FM data bus
L15 FM_D8 1.8-V FM data bus
L12 FM_D9 1.8-V FM data bus
M16 FM_D10 1.8-V FM data bus
L13 FM_D11 1.8-V FM data bus
M15 FM_D12 1.8-V FM data bus
L14 FM_D13 1.8-V FM data bus
N16 FM_D14 1.8-V FM data bus
M13 FM_D15 1.8-V FM data bus
N15 FORCE_FAN 1.8-V DIP switch to enable or disable the fan
K5 FPGA_CEN 2.5-V FPGA chip enable
K1 FPGA_CONF_DONE 2.5-V FPGA configuration done LED
D3 FPGA_CONFIG_D0 2.5-V FPGA configuration data
C2 FPGA_CONFIG_D1 2.5-V FPGA configuration data
C3 FPGA_CONFIG_D2 2.5-V FPGA configuration data
E3 FPGA_CONFIG_D3 2.5-V FPGA configuration data
D2 FPGA_CONFIG_D4 2.5-V FPGA configuration data
E4 FPGA_CONFIG_D5 2.5-V FPGA configuration data
D1 FPGA_CONFIG_D6 2.5-V FPGA configuration data
E5 FPGA_CONFIG_D7 2.5-V FPGA configuration data
F3 FPGA_CONFIG_D8 2.5-V FPGA configuration data
E1 FPGA_CONFIG_D9 2.5-V FPGA configuration data
F4 FPGA_CONFIG_D10 2.5-V FPGA configuration data
F2 FPGA_CONFIG_D11 2.5-V FPGA configuration data
F1 FPGA_CONFIG_D12 2.5-V FPGA configuration data
F6 FPGA_CONFIG_D13 2.5-V FPGA configuration data
G2 FPGA_CONFIG_D14 2.5-V FPGA configuration data
G3 FPGA_CONFIG_D15 2.5-V FPGA configuration data
N3 FPGA_CVP_CONFDONE 2.5-V FPGA configuration via protocol done LED
J3 FPGA_DCLK 2.5-V FPGA configuration clock
B10 FPGA_MSEL0 2.5-V FPGA mode select 0
B3 FPGA_MSEL1 2.5-V FPGA mode select 1
C10 FPGA_MSEL2 2.5-V FPGA mode select 2
C12 FPGA_MSEL3 2.5-V FPGA mode select 3
C6 FPGA_MSEL4 2.5-V FPGA mode select 4
N1 FPGA_NCONFIG 2.5-V FPGA configuration active
J4 FPGA_NSTATUS 2.5-V FPGA configuration ready
H1 FPGA_PR_DONE 2.5-V FPGA partial reconfiguration done
Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 3 of 5)
Board
Reference (U32)
Schematic Signal Name I/O Standard Description