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Altera Cyclone V GT FPGA Development Board User Manual

Page 18

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2–10

Chapter 2: Board Components

MAX V CPLD 5M2210 System Controller

Cyclone V GT FPGA Development Board

September 2014

Altera Corporation

Reference Manual

P2

FPGA_PR_ERROR

2.5-V

FPGA partial reconfiguration error

E2

FPGA_PR_READY

2.5-V

FPGA partial reconfiguration ready

F5

FPGA_PR_REQUEST

2.5-V

FPGA partial reconfiguration request

B8

HSMA_PRSNTN

2.5-V

HSMC port A present

A8

HSMB_PRSNTN

2.5-V

HSMC port B present

M5

JTAG_BLASTER_TDI

2.5-V

MAX V CPLD JTAG chain data out

L6

JTAG_EPM2210_TDI

2.5-V

MAX V CPLD JTAG chain data in

P3

JTAG_TCK

2.5-V

JTAG chain clock

N4

JTAG_TMS

2.5-V

JTAG chain mode select

P11

M570_CLOCK

1.8-V

25-MHz clock to embedded USB-Blaster II for sending
FACTORY command

P12

M570_PCIE_JTAG_EN

1.8-V

Low signal to disable the embedded USB-Blaster II when PCI
Express is the master to the JTAG chain

H2

MAX_AS_CONF

2.5-V

MAX V active serial configuration

T11

MAX_CLK

2.5-V

Clock source from the FPGA PLL

E11

MAX_CONF_DONE

2.5-V

Embedded USB-Blaster II configuration done LED

R10

MAX_CSN

1.8-V

FM bus MAX V chip select

A4

MAX_ERROR

2.5-V

FPGA configuration error LED

A6

MAX_LOAD

2.5-V

FPGA configuration active LED

M10

MAX_OEN

1.8-V

FM bus MAX V output enable

M9

MAX_RESETN

1.8-V

MAX V reset push button

N10

MAX_WEN

1.8-V

FM bus MAX V write enable

B7

OVERTEMP

2.5-V

Temperature monitor fan enable

D12

PGM_CONFIG

2.5-V

Load the flash memory image identified by the PGM LEDs

B14

PGM_LED0

2.5-V

Flash memory PGM select indicator 0

C13

PGM_LED1

2.5-V

Flash memory PGM select indicator 1

B16

PGM_LED2

2.5-V

Flash memory PGM select indicator 2

B13

PGM_SEL

2.5-V

Toggles the PGM_LED[2:0] LED sequence

D5

SDI_A_RX_BYPASS

2.5-V

SDI equalization bypass

E8

SDI_A_RX_EN

2.5-V

SDI receive enable

D11

SDI_A_TX_EN

2.5-V

SDI transmit enable

E7

SENSE_CSN

2.5-V

Power monitor chip select

A5

SENSE_SCK

2.5-V

Power monitor SPI clock

D7

SENSE_SDI

2.5-V

Power monitor SPI data in

B6

SENSE_SDO

2.5-V

Power monitor SPI data out

A10

SI570_EN

2.5-V

Variable voltage oscillator enable

D4

SI571_EN

2.5-V

SDI variable voltage oscillator enable

R4

USB_CFG0

1.8-V

Embedded USB-Blaster II interface. Reserved for future use

T4

USB_CFG1

1.8-V

Embedded USB-Blaster II interface. Reserved for future use

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 4 of 5)

Board

Reference (U32)

Schematic Signal Name

I/O Standard

Description