Altera Cyclone V GT FPGA Development Board - Manual (Page 26)

2–18 Chapter 2: Board Components
Clock Circuitry
Cyclone V GT FPGA Development Board September 2014 Altera Corporation
Reference Manual
MAX V Reset Push Button
The MAX V reset push button, MAX_RESETn (S7), is an input to the MAX V CPLD
5M2210 System Controller. This push button is the default reset for the CPLD logic.
Program Configuration Push Button
The program configuration push button, PGM_CONFIG (S5), is an input to the MAX V
CPLD 5M2210 System Controller. This input forces a FPGA reconfiguration from the
flash memory. The location in the flash memory is based on the settings of
PGM_LED[2:0]
, which is controlled by the program select push button, PGM_SEL. Valid
settings include PGM_LED0, PGM_LED1, or PGM_LED2 on the three pages in flash memory
reserved for FPGA designs.
Program Select Push Button
The program select push button, PGM_SEL (S6), is an input to the MAX V CPLD System
Controller. This push button toggles the PGM_LED[2:0]sequence that selects which
location in the flash memory is used to configure the FPGA. Refer to
Table 2–6 for the
PGM_LED[2:0] sequence definitions.
Clock Circuitry
This section describes the board's clock inputs and outputs.
On-Board Oscillators
The development board includes oscillators with a frequency of 50 MHz, 125 MHz,
148.50 MHz, and two programmable oscillators with a default frequencies of
100 MHz. The programmable oscillators have a frequency range from 10–810 MHz
and can be programmed through the clock control application in the
examples/board_test_system
directory.