Altera Cyclone V GT FPGA Development Board - Manual (Page 22)

2–14 Chapter 2: Board Components
FPGA Configuration
Cyclone V GT FPGA Development Board September 2014 Altera Corporation
Reference Manual
Figure 2–4 shows the PFL configuration.
f For more information on the following topics, refer to the respective documents:
■ Board Update Portal, PFL design, and flash memory map storage, refer to the
Cyclone V GT FPGA Development Kit User Guide .
■ PFL megafunction, refer to Parallel Flash Loader Megafunction User Guide.
FPGA Programming over External USB-Blaster
The JTAG chain header provides another method for configuring the FPGA using an
external USB-Blaster device with the Quartus II Programmer running on a PC. To
prevent contention between the JTAG masters, the embedded USB-Blaster is
automatically disabled when you connect an external USB-Blaster to the JTAG chain
through the JTAG chain header.
Figure 2–4. PFL Configuration
MAX V CPLD
5M2210 System Controller
Cyclone V FPGA
FPGA_DATA [15:0]
FPGA_DCLK
FLASH_A [26:1]
FLASH_D [15:0]
DATA [15:0]
DCLK
nSTATUS
nCONFIG
CONF_DONE
MSEL1
MSEL2
MSEL4
MSEL0
MSEL3
MSEL[4:0] also
connects to the
MAX V CPLD
2.5 V
1 k Ω
1 k Ω
nCE
CFI Flash
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_A [26:1]
FLASH_D [15:0]
FLASH_CEn
FLASH_OEn
FLASH_WEn
FLASH_WPn
FLASH_ADVn
FPGA_nCONFIG
FPGA_CONF_DONE
FLASH_RYBSYn
FLASH_RYBSYn
FPGA_nSTATUS
1.8 V
10 k Ω
FLASH_ADVn
FLASH_CLK
FLASH_CLK
FLASH_RSTn
FLASH_RESETn
PS Port
Flash Interface
100 Ω 56.2 Ω
56.2 Ω
50 MHz
100 MHz
2.5 V
2.5 V 2.5 V
MAX_ERROR
MAX_LOAD
MAX_CONF_DONE
ASSP_MODE
FACTORY_USER
CLK_ENABLE
CLK_SEL
MAX_RESETn
CPU_RESETn
PGM_CONFIG
PGM_SEL
PGM_LED0
PGM_LED1
PGM_LED2
DIP Switch
DIP Switch
10 k Ω DNI