Altera Cyclone V GT FPGA Development Board - Manual (Page 55)

Chapter 2: Board Components 2–47
Memory
September 2014 Altera Corporation Cyclone V GT FPGA Development Board
Reference Manual
K9 DDR3B_CKE AF32 1.5-V SSTL Class I Column address select
J7 DDR3B_CLK_P R30
Differential 1.5-V SSTL
Class I
Differential output clock
K7 DDR3B_CLK_N R29
Differential 1.5-V SSTL
Class I
Differential output clock
L2 DDR3B_CSN V27 1.5-V SSTL Class I Chip select
E7 DDR3B_DM6 L31 1.5-V SSTL Class I Write mask byte lane
D3 DDR3B_DM7 H28 1.5-V SSTL Class I Write mask byte lane
E3 DDR3B_DQ48 N28 1.5-V SSTL Class I Data bus byte lane 6
F7 DDR3B_DQ49 L30 1.5-V SSTL Class I Data bus byte lane 6
F2 DDR3B_DQ50 P30 1.5-V SSTL Class I Data bus byte lane 6
F8 DDR3B_DQ51 K30 1.5-V SSTL Class I Data bus byte lane 6
H3 DDR3B_DQ52 J32 1.5-V SSTL Class I Data bus byte lane 6
H8 DDR3B_DQ53 H32 1.5-V SSTL Class I Data bus byte lane 6
G2 DDR3B_DQ54 M31 1.5-V SSTL Class I Data bus byte lane 6
H7 DDR3B_DQ55 H31 1.5-V SSTL Class I Data bus byte lane 6
D7 DDR3B_DQ56 G30 1.5-V SSTL Class I Data bus byte lane 7
C3 DDR3B_DQ57 K29 1.5-V SSTL Class I Data bus byte lane 7
C8 DDR3B_DQ58 G31 1.5-V SSTL Class I Data bus byte lane 7
C2 DDR3B_DQ59 M30 1.5-V SSTL Class I Data bus byte lane 7
A7 DDR3B_DQ60 J30 1.5-V SSTL Class I Data bus byte lane 7
A2 DDR3B_DQ61 M29 1.5-V SSTL Class I Data bus byte lane 7
B8 DDR3B_DQ62 J29 1.5-V SSTL Class I Data bus byte lane 7
A3 DDR3B_DQ63 L28 1.5-V SSTL Class I Data bus byte lane 7
F3 DDR3B_DQS_P6 R23
Differential 1.5-V SSTL
Class I
Data strobe P byte lane 6
G3 DDR3B_DQS_N6 R24
Differential 1.5-V SSTL
Class I
Data strobe N byte lane 6
C7 DDR3B_DQS_P7 P24
Differential 1.5-V SSTL
Class I
Data strobe P byte lane 7
B7 DDR3B_DQS_N7 P25
Differential 1.5-V SSTL
Class I
Data strobe N byte lane 7
K1 DDR3B_ODT AA32 1.5-V SSTL Class I On-die termination enable
J3 DDR3B_RASN Y32 1.5-V SSTL Class I Row address select
T2 DDR3B_RESETN AG31 1.5-V SSTL Class I Reset
L3 DDR3B_WEN AM34 1.5-V SSTL Class I Write enable
L8 DDR3B_ZQ03 — 1.5-V SSTL Class I ZQ impedance calibration
Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 6 of 6)
Board Reference
Schematic
Signal Name
Cyclone V GT
Pin Number
I/O Standard Description