Altera Cyclone V GT FPGA Development Board - Manual (Page 53)

Chapter 2: Board Components 2–45
Memory
September 2014 Altera Corporation Cyclone V GT FPGA Development Board
Reference Manual
T2 DDR3B_RESETN AG31 1.5-V SSTL Class I Reset
L3 DDR3B_WEN AM34 1.5-V SSTL Class I Write enable
L8 DDR3B_ZQ2 — 1.5-V SSTL Class I ZQ impedance calibration
DDR3 x16 (U8)
N3 DDR3B_A0 H29 1.5-V SSTL Class I Address bus
P7 DDR3B_A1 K28 1.5-V SSTL Class I Address bus
P3 DDR3B_A2 K34 1.5-V SSTL Class I Address bus
N2 DDR3B_A3 L32 1.5-V SSTL Class I Address bus
P8 DDR3B_A4 R32 1.5-V SSTL Class I Address bus
P2 DDR3B_A5 R33 1.5-V SSTL Class I Address bus
R8 DDR3B_A6 N32 1.5-V SSTL Class I Address bus
R2 DDR3B_A7 G33 1.5-V SSTL Class I Address bus
T8 DDR3B_A8 AE34 1.5-V SSTL Class I Address bus
R3 DDR3B_A9 L27 1.5-V SSTL Class I Address bus
L7 DDR3B_A10 V33 1.5-V SSTL Class I Address bus
R7 DDR3B_A11 U33 1.5-V SSTL Class I Address bus
N7 DDR3B_A12 T31 1.5-V SSTL Class I Address bus
T3 DDR3B_A13 T30 1.5-V SSTL Class I Address bus
M2 DDR3B_BA0 J31 1.5-V SSTL Class I Bank address bus
N8 DDR3B_BA1 N29 1.5-V SSTL Class I Bank address bus
M3 DDR3B_BA2 P27 1.5-V SSTL Class I Bank address bus
K3 DDR3B_CASN N27 1.5-V SSTL Class I Row address select
K9 DDR3B_CKE AF32 1.5-V SSTL Class I Column address select
J7 DDR3B_CLK_P R30
Differential 1.5-V SSTL
Class I
Differential output clock
K7 DDR3B_CLK_N R29
Differential 1.5-V SSTL
Class I
Differential output clock
L2 DDR3B_CSN V27 1.5-V SSTL Class I Chip select
E7 DDR3B_DM4 M33 1.5-V SSTL Class I Write mask byte lane
D3 DDR3B_DM5 K32 1.5-V SSTL Class I Write mask byte lane
E3 DDR3B_DQ32 T32 1.5-V SSTL Class I Data bus byte lane 4
F7 DDR3B_DQ33 N33 1.5-V SSTL Class I Data bus byte lane 4
F2 DDR3B_DQ34 T33 1.5-V SSTL Class I Data bus byte lane 4
F8 DDR3B_DQ35 L33 1.5-V SSTL Class I Data bus byte lane 4
H3 DDR3B_DQ36 T28 1.5-V SSTL Class I Data bus byte lane 4
H8 DDR3B_DQ37 J34 1.5-V SSTL Class I Data bus byte lane 4
G2 DDR3B_DQ38 T27 1.5-V SSTL Class I Data bus byte lane 4
H7 DDR3B_DQ39 M34 1.5-V SSTL Class I Data bus byte lane 4
D7 DDR3B_DQ40 K33 1.5-V SSTL Class I Data bus byte lane 5
Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 6)
Board Reference
Schematic
Signal Name
Cyclone V GT
Pin Number
I/O Standard Description