Altera Cyclone V GT FPGA Development Board - Manual (Page 14)

2–6 Chapter 2: Board Components
MAX V CPLD 5M2210 System Controller
Cyclone V GT FPGA Development Board September 2014 Altera Corporation
Reference Manual
Table 2–4 lists the Cyclone V GT device transceiver count and usage by function on
the board.
MAX V CPLD 5M2210 System Controller
The board utilizes the 5M2210 System Controller, an Altera MAX V CPLD, for the
following purposes:
■ FPGA configuration from flash
■ Power measurement
■ Control and status registers (CSRs) for remote system update
SDI video port 2.5-V CMOS + XCVR 6 —
Push buttons 1.5-V CMOS 4 —
DIP switches 1.5-V CMOS 8 —
Character LCD 1.5-V CMOS 2 —
LEDs 1.5-V CMOS 8 —
SMA CMOS 1 —
Clock or Oscillators 1.8-V CMOS + LVDS 9
Four differential clocks, 1
1 single-ended
ASSP 1.5-V CMOS 8 —
Configuration — 30 —
Total I/O Used: 540
Table 2–3. Cyclone V GT Device I/O Pin Count
Function I/O Standard I/O Count Special Clock Pins
Table 2–4. Cyclone V GT Transceivers
Function Count
HSMA port 3
HSMA port or SDI (supports HSMA by default) 1
HSMB port 4
PCI Express x4 port 4
Total Transceivers 12