Altera Cyclone V GT FPGA Development Board - Manual (Page 16)

2–8 Chapter 2: Board Components
MAX V CPLD 5M2210 System Controller
Cyclone V GT FPGA Development Board September 2014 Altera Corporation
Reference Manual
N7 FLASH_ADVN 1.8-V FM bus flash memory address valid
R5 FLASH_CEN 1.8-V FM bus flash memory chip enable
R6 FLASH_CLK 1.8-V FM bus flash memory clock
M6 FLASH_OEN 1.8-V FM bus flash memory output enable
T5 FLASH_RDYBSYN 1.8-V FM bus flash memory ready
P7 FLASH_RESETN 1.8-V FM bus flash memory reset
N6 FLASH_WEN 1.8-V FM bus flash memory write enable
C14 FM_A1 1.8-V FM address bus
C15 FM_A2 1.8-V FM address bus
E13 FM_A3 1.8-V FM address bus
E12 FM_A4 1.8-V FM address bus
D15 FM_A5 1.8-V FM address bus
F14 FM_A6 1.8-V FM address bus
D16 FM_A7 1.8-V FM address bus
F13 FM_A8 1.8-V FM address bus
E15 FM_A9 1.8-V FM address bus
E16 FM_A10 1.8-V FM address bus
F15 FM_A11 1.8-V FM address bus
G14 FM_A12 1.8-V FM address bus
F16 FM_A13 1.8-V FM address bus
G13 FM_A14 1.8-V FM address bus
G15 FM_A15 1.8-V FM address bus
G12 FM_A16 1.8-V FM address bus
G16 FM_A17 1.8-V FM address bus
H14 FM_A18 1.8-V FM address bus
H15 FM_A19 1.8-V FM address bus
H13 FM_A20 1.8-V FM address bus
H16 FM_A21 1.8-V FM address bus
J13 FM_A22 1.8-V FM address bus
R3 FM_A23 1.8-V FM address bus
P5 FM_A24 1.8-V FM address bus
T2 FM_A25 1.8-V FM address bus
P4 FM_A26 1.8-V FM address bus
J14 FM_D0 1.8-V FM data bus
J15 FM_D1 1.8-V FM data bus
K16 FM_D2 1.8-V FM data bus
K13 FM_D3 1.8-V FM data bus
K15 FM_D4 1.8-V FM data bus
K14 FM_D5 1.8-V FM data bus
Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 2 of 5)
Board
Reference (U32)
Schematic Signal Name I/O Standard Description