Altera Cyclone V GT FPGA Development Board - Manual (Page 54)

2–46 Chapter 2: Board Components
Memory
Cyclone V GT FPGA Development Board September 2014 Altera Corporation
Reference Manual
C3 DDR3B_DQ41 N31 1.5-V SSTL Class I Data bus byte lane 5
C8 DDR3B_DQ42 G34 1.5-V SSTL Class I Data bus byte lane 5
C2 DDR3B_DQ43 R28 1.5-V SSTL Class I Data bus byte lane 5
A7 DDR3B_DQ44 H33 1.5-V SSTL Class I Data bus byte lane 5
A2 DDR3B_DQ45 P32 1.5-V SSTL Class I Data bus byte lane 5
B8 DDR3B_DQ46 H34 1.5-V SSTL Class I Data bus byte lane 5
A3 DDR3B_DQ47 R27 1.5-V SSTL Class I Data bus byte lane 5
F3 DDR3B_DQS_P4 U23
Differential 1.5-V SSTL
Class I
Data strobe P byte lane 4
G3 DDR3B_DQS_N4 T23
Differential 1.5-V SSTL
Class I
Data strobe N byte lane 4
C7 DDR3B_DQS_P5 T25
Differential 1.5-V SSTL
Class I
Data strobe P byte lane 5
B7 DDR3B_DQS_N5 R25
Differential 1.5-V SSTL
Class I
Data strobe N byte lane 5
K1 DDR3B_ODT AA32 1.5-V SSTL Class I On-die termination enable
J3 DDR3B_RASN Y32 1.5-V SSTL Class I Row address select
T2 DDR3B_RESETN AG31 1.5-V SSTL Class I Reset
L3 DDR3B_WEN AM34 1.5-V SSTL Class I Write enable
L8 DDR3B_ZQ03 — 1.5-V SSTL Class I ZQ impedance calibration
DDR3 x16 (U15)
N3 DDR3B_A0 H29 1.5-V SSTL Class I Address bus
P7 DDR3B_A1 K28 1.5-V SSTL Class I Address bus
P3 DDR3B_A2 K34 1.5-V SSTL Class I Address bus
N2 DDR3B_A3 L32 1.5-V SSTL Class I Address bus
P8 DDR3B_A4 R32 1.5-V SSTL Class I Address bus
P2 DDR3B_A5 R33 1.5-V SSTL Class I Address bus
R8 DDR3B_A6 N32 1.5-V SSTL Class I Address bus
R2 DDR3B_A7 G33 1.5-V SSTL Class I Address bus
T8 DDR3B_A8 AE34 1.5-V SSTL Class I Address bus
R3 DDR3B_A9 L27 1.5-V SSTL Class I Address bus
L7 DDR3B_A10 V33 1.5-V SSTL Class I Address bus
R7 DDR3B_A11 U33 1.5-V SSTL Class I Address bus
N7 DDR3B_A12 T31 1.5-V SSTL Class I Address bus
T3 DDR3B_A13 T30 1.5-V SSTL Class I Address bus
M2 DDR3B_BA0 J31 1.5-V SSTL Class I Bank address bus
N8 DDR3B_BA1 N29 1.5-V SSTL Class I Bank address bus
M3 DDR3B_BA2 P27 1.5-V SSTL Class I Bank address bus
K3 DDR3B_CASN N27 1.5-V SSTL Class I Row address select
Table 2–29. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 6)
Board Reference
Schematic
Signal Name
Cyclone V GT
Pin Number
I/O Standard Description