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AMD Geode SC1201 User Manual

Page 275

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AMD Geode™ SC1200/SC1201 Processor Data Book

275

Core Logic Module - Audio Registers - Function 3

32579B

Offset 40h

Audio Bus Master 4 Command Register (R/W)

Reset Value: 00h

Audio Bus Master 4: Output to codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memory Offset 08h[19] selects slot).

7:4

Reserved. Must be set to 0. Must return 0 on reads.

3

Read or Write Control. Set the transfer direction of Audio Bus Master 4.

0: PCI reads are performed.

1: PCI writes are performed.

This bit must be set to 0 (read) and should not be changed when the bus master is active.

2:1

Reserved. Must be set to 0. Must return 0 on reads.

0

Bus Master Control. Controls the state of the Audio Bus Master 4.

0: Disable.

1: Enable.

Setting this bit to 1 enables the bus master to begin data transfers. When writing 0 to this bit, the bus master must be either
paused or have reached EOT. Writing 0 to this bit while the bus master is operating, results in unpredictable behavior (and
may crash the bus master state machine). The only recovery from this condition is a PCI reset.

Offset 41h

Audio Bus Master 4 SMI Status Register (RC)

Reset Value: 00h

Audio Bus Master 4: Output to codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memory Offset 08h[19] selects slot).

7:2

Reserved.

1

Bus Master Error. Indicates if hardware encountered a second EOP before software cleared the first.

0: No.

1: Yes.

If hardware encounters a second EOP (end of page) before software cleared the first, it causes the bus master to pause
until this register is read to clear the error.

0

End of Page. Bus master transferred data which is marked by the EOP bit in the PRD table (bit 30).

0: No.

1: Yes.

Offset 42h-43h

Not Used

Offset 44h-47h

Audio Bus Master 4 PRD Table Address (R/W)

Reset Value: 00000000h

Audio Bus Master 4: Output to codec; 16-Bit; Slot 6 or 11 (F3BAR0+Memory Offset 08h[19] selects slot).

31:2

Pointer to the Physical Region Descriptor Table. This register is a PRD table pointer for Audio Bus Master 4.

When written, this register points to the first entry in a PRD table. Once Audio Bus Master 4 is enabled (Command Register
bit 0 = 1), it loads the pointer and updates this register (by adding 08h) so that it points to the next PRD.

When read, this register points to the next PRD.

1:0

Reserved. Must be set to 0.

Note:

The Physical Region Descriptor (PRD) table consists of one or more entries - each describing a memory region to or from
which data is to be transferred. Each entry consists of two DWORDs.

DWORD 0:

[31:0]

= Memory Region Physical Base Address

DWORD 1:

31

= End of Table Flag

30

= End of Page Flag

29

= Loop Flag (JMP)

[28:16]

= Reserved (0)

[15:0]

= Byte Count of the Region (Size)

Table 6-38. F3BAR0+Memory Offset: Audio Configuration Registers (Continued)

Bit

Description

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