Table 6-20 – AMD Geode SC1201 User Manual
Page 182
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182
AMD Geode™ SC1200/SC1201 Processor Data Book
Core Logic Module - Register Summary
32579B
Table 6-20. F2: PCI Header Registers for IDE Controller Support Summary
F2 Index
Width
(Bits)
Type
Name
Reset
Value
Reference
00h-01h
16
RO
Vendor Identification Register
100Bh
02h-03h
16
RO
Device Identification Register
0502h
04h-05h
16
R/W
PCI Command Register
0000h
06h-07h
16
RO
PCI Status Register
0280h
08h
8
RO
Device Revision ID Register
01h
09h-0Bh
24
RO
PCI Class Code Register
010180h
0Ch
8
RO
PCI Cache Line Size Register
00h
0Dh
8
RO
PCI Latency Timer Register
00h
0Eh
8
RO
PCI Header Type Register
00h
0Fh
8
RO
PCI BIST Register
00h
10h-13h
32
RO
Base Address Register 0 (F2BAR0) — Reserved for possible
future use by the Core Logic module.
00000000h
14h-17h
32
RO
Base Address Register 1 (F2BAR1) — Reserved for possible
future use by the Core Logic module.
00000000h
18h-1Bh
32
RO
Base Address Register 2 (F2BAR2) — Reserved for possible
future use by the Core Logic module.
00000000h
1Ch-1Fh
32
RO
Base Address Register 3 (F2BAR3) — Reserved for possible
future use by the Core Logic module.
00000000h
20h-23h
32
R/W
Base Address Register 4 (F2BAR4) — Sets the base address for
the I/O mapped Bus Master IDE Registers (summarized in Table
6-21)
00000001h
24h-2Bh
---
---
Reserved
00h
2Ch-2Dh
16
RO
Subsystem Vendor ID
100Bh
2Eh-2Fh
16
RO
Subsystem ID
0502h
30h-3Fh
---
---
Reserved
00h
40h-43h
32
R/W
Channel 0 Drive 0 PIO Register
00009172h
44h-47h
32
R/W
Channel 0 Drive 0 DMA Control Register
00077771h
48h-4Bh
32
R/W
Channel 0 Drive 1 PIO Register
00009172h
4Ch-4Fh
32
R/W
Channel 0 Drive 1 DMA Control Register
00077771h
50h-53h
32
R/W
Channel 1 Drive 0 PIO Register
00009172h
54h-57h
32
R/W
Channel 1 Drive 0 DMA Control Register
00077771h
58h-5Bh
32
R/W
Channel 1 Drive 1 PIO Register
00009172h
5Ch-5Fh
32
R/W
Channel 1 Drive 1 DMA Control Register
00077771h
60h-FFh
---
---
Reserved
00h