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AMD Geode SC1201 User Manual

Page 244

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244

AMD Geode™ SC1200/SC1201 Processor Data Book

Core Logic Module - SMI Status and ACPI Registers - Function 1

32579B

21

EXT_SMI5 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI5.

0: No.

1: Yes.

To enable SMI generation, set bit 5 to 1.

20

EXT_SMI4 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI4.

0: No.

1: Yes.

To enable SMI generation, set bit 4 to 1.

19

EXT_SMI3 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI3.

0: No.

1: Yes.

To enable SMI generation, set bit 3 to 1.

18

EXT_SMI2 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI2.

0: No.

1: Yes.

To enable SMI generation, set bit 2 to 1.

17

EXT_SMI1 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI1.

0: No.

1: Yes.

To enable SMI generation, set bit 1 to 1.

16

EXT_SMI0 SMI Status. (Read to Clear) Indicates whether or not an SMI was caused by an assertion of EXT_SMI0.

0: No.

1: Yes.

To enable SMI generation, set bit 0 to 1.

15

EXT_SMI7 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI7.

0: No.

1: Yes.

To enable SMI generation, set bit 7 to 1.

14

EXT_SMI6 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI6.

0: No.

1: Yes.

To enable SMI generation, set bit 6 to 1.

13

EXT_SMI5 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI5.

0: No.

1: Yes.

To enable SMI generation, set bit 5 to 1.

12

EXT_SMI4 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI4.

0: No.

1: Yes.

To enable SMI generation, set bit 4 to 1.

11

EXT_SMI3 SMI Status. (Read Only) Indicates whether or not an SMI was caused by an assertion of EXT_SMI3.

0: No.

1: Yes.

To enable SMI generation, set bit 3 to 1.

Table 6-33. F1BAR0+I/O Offset: SMI Status Registers (Continued)

Bit

Description

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