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Table 6-28, Isa legacy i/o register summary – AMD Geode SC1201 User Manual

Page 188

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188

AMD Geode™ SC1200/SC1201 Processor Data Book

Core Logic Module - Register Summary

32579B

Table 6-28. ISA Legacy I/O Register Summary

I/O Port

Type

Name

Reference

DMA Channel Control Registers (Table 6-43)

000h

R/W

DMA Channel 0 Address Register

Page 296

001h

R/W

DMA Channel 0 Transfer Count Register

Page 296

002h

R/W

DMA Channel 1 Address Register

Page 296

003h

R/W

DMA Channel 1 Transfer Count Register

Page 296

004h

R/W

DMA Channel 2 Address Register

Page 296

005h

R/W

DMA Channel 2 Transfer Count Register

Page 296

006h

R/W

DMA Channel 3 Address Register

Page 296

007h

R/W

DMA Channel 3 Transfer Count Register

Page 296

008h

Read

DMA Status Register, Channels 3:0

Page 296

Write

DMA Command Register, Channels 3:0

Page 297

009h

WO

Software DMA Request Register, Channels 3:0

Page 297

00Ah

W

DMA Channel Mask Register, Channels 3:0

Page 297

00Bh

WO

DMA Channel Mode Register, Channels 3:0

Page 298

00Ch

WO

DMA Clear Byte Pointer Command, Channels 3:0

Page 298

00Dh

WO

DMA Master Clear Command, Channels 3:0

Page 298

00Eh

WO

DMA Clear Mask Register Command, Channels 3:0

Page 298

00Fh

WO

DMA Write Mask Register Command, Channels 3:0

Page 298

0C0h

R/W

DMA Channel 4 Address Register (Not used)

Page 298

0C2h

R/W

DMA Channel 4 Transfer Count Register (Not Used)

Page 298

0C4h

R/W

DMA Channel 5 Address Register

Page 298

0C6h

R/W

DMA Channel 5 Transfer Count Register

Page 298

0C8h

R/W

DMA Channel 6 Address Register

Page 298

0CAh

R/W

DMA Channel 6 Transfer Count Register

Page 298

0CCh

R/W

DMA Channel 7 Address Register

Page 298

0CEh

R/W

DMA Channel 7 Transfer Count Register

Page 298

0D0h

Read

DMA Status Register, Channels 7:4

Page 299

Write

DMA Command Register, Channels 7:4

Page 299

0D2h

WO

Software DMA Request Register, Channels 7:4

Page 300

0D4h

W

DMA Channel Mask Register, Channels 7:4

Page 300

0D6h

WO

DMA Channel Mode Register, Channels 7:4

Page 300

0D8h

WO

DMA Clear Byte Pointer Command, Channels 7:4

Page 300

0DAh

WO

DMA Master Clear Command, Channels 7:4

Page 300

0DCh

WO

DMA Clear Mask Register Command, Channels 7:4

Page 300

0DEh

WO

DMA Write Mask Register Command, Channels 7:4

Page 301

DMA Page Registers (Table 6-44)

081h

R/W

DMA Channel 2 Low Page Register

Page 301

082h

R/W

DMA Channel 3 Low Page Register

Page 301

083h

R/W

DMA Channel 1 Low Page Register

Page 301

087h

R/W

DMA Channel 0 Low Page Register

Page 301

089h

R/W

DMA Channel 6 Low Page Register

Page 301

08Ah

R/W

DMA Channel 7 Low Page Register

Page 301

08Bh

R/W

DMA Channel 5 Low Page Register

Page 301

08Fh

R/W

Sub-ISA Refresh Low Page Register

Page 301

481h

R/W

DMA Channel 2 High Page Register

Page 301

482h

R/W

DMA Channel 3 High Page Register

Page 301

483h

R/W

DMA Channel 1 High Page Register

Page 301

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