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5 ldn 05h and 06h - access.bus ports 1 and 2, Table 5-13, Relevant acb1 and acb2 registers – AMD Geode SC1201 User Manual

Page 103: Table 5-14, Acb1 and acb2 configuration register

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AMD Geode™ SC1200/SC1201 Processor Data Book

103

SuperI/O Module

32579B

5.4.2.5

LDN 05h and 06h - ACCESS.bus Ports 1 and 2

ACCESS.bus ports 1 and 2 (ACB1 and ACB2) are identi-
cal. Each ACB is a two-wire synchronous serial interface
compatible with the ACCESS.bus physical layer. ACB1 and
ACB2 use a 24 MHz internal clock. Six runtime registers for
each ACCESS.bus are described in Section 5.7
"ACCESS.bus Interface" on page 121.

ACB1 is designated as LDN 05h and ACB2 as LDN 06h.
Table 5-13 lists the configuration registers which affect the
ACCESS.bus ports. Only the last register (F0h) is
described here (Table 5-14). See Table 5-3 "Standard Con-
figuration Registers" on page 95 f
or descriptions of the oth-
ers.

Table 5-13. Relevant ACB1 and ACB2 Registers

Index

Type

Configuration Register or Action

Reset

Value

30h

R/W

Activate. See also bit 0 of the SIOCF1 register

00h

60h

R/W

Base Address MSB register.

00h

61h

R/W

Base Address LSB register. Bits [2:0] (for A[2:0]) are RO, 000b.

00h

70h

R/W

Interrupt Number.

00h

71h

R/W

Interrupt Type. Bit 1 is R/W. Other bits are RO.

03h

74h

RO

Report no DMA assignment.

04h

75h

RO

Report no DMA assignment.

04h

F0h

R/W

ACB1 and ACB2 Configuration register.

00h

Table 5-14. ACB1 and ACB2 Configuration Register

Bit

Description

Index F0h

ACB1 and ACB2 Configuration Register (R/W)

This register is reset by hardware to 00h.

7:3

Reserved.

2

Internal Pull-Up Enable.

0: No internal pull-up resistors on AB1C/AB2C and AB1D/AB2D. (Default)

1: Internal pull-up resistors on AB1C/AB2C and AB1D/AB2D.

1:0

Reserved.

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