AMD Geode SC1201 - Manual (Page 121)

AMD Geode™ SC1200/SC1201 Processor Data Book 121
SuperI/O Module 32579B
5.7 ACCESS.bus Interface
The SC1200/SC1201 processor has two ACCESS.bus
(ACB) controllers. ACB is a two-wire synchronous serial
interface compatible with the ACCESS.bus physical layer,
Intel's SMBus, and Philips’ I
2
C. The ACB can be config-
ured as a bus master or slave, and can maintain bidirec-
tional communication with both multiple master and slave
devices. As a slave device, the ACB may issue a request
to become the bus master.
The ACB allows easy interfacing to a wide range of low-
cost memories and I/O devices, including: EEPROMs,
SRAMs, timers, ADC, DAC, clock chips and peripheral
drivers.
The ACCESS.bus protocol uses a two-wire interface for
bidirectional communication between the ICs connected to
the bus. The two interface lines are the Serial Data Line
(AB1D and AB2D) and the Serial Clock Line (AB1C and
AB2C). (Here after referred to as ABD and ABC unless oth-
erwise specified.) These lines should be connected to a
positive supply via an internal or external pull-up resistor,
and remain high even when the bus is idle.
Each IC has a unique address and can operate as a trans-
mitter or a receiver (though some peripherals are only
receivers).
During data transactions, the master device initiates the
transaction, generates the clock signal and terminates the
transaction. For example, when the ACB initiates a data
transaction with an attached ACCESS.bus compliant
peripheral, the ACB becomes the master. When the
peripheral responds and transmits data to the ACB, their
master/slave (data transaction initiator and clock genera-
tor) relationship is unchanged, even though their transmit-
ter/receiver functions are reversed.
This section describes the general ACB functional block. A
device may include a different implementation. For device
specific implementation, see Section 5.4.2.5 "LDN 05h and
06h - ACCESS.bus Ports 1 and 2" on page 103.
5.7.1 Data Transactions
One data bit is transferred during each clock pulse. Data is
sampled during the high state of the serial clock (ABC).
Consequently, throughout the clock’s high period, the data
should remain stable (see Figure 5-13). Any changes on
the ABD line during the high state of the ABC and in the
middle of a transaction aborts the current transaction. New
data should be sent during the low ABC state. This protocol
permits a single data line to transfer both command/control
information and data, using the synchronous serial clock.
Each data transaction is composed of a Start Condition, a
number of byte transfers (set by the software) and a Stop
Condition to terminate the transaction. Each byte is trans-
ferred with the most significant bit first, and after each byte
(8 bits), an Acknowledge signal must follow. The following
sections provide further details of this process.
During each clock cycle, the slave can stall the master
while it handles the previous data or prepares new data.
This can be done for each bit transferred, or on a byte
boundary, by the slave holding ABC low to extend the
clock-low period. Typically, slaves extend the first clock
cycle of a transfer if a byte read has not yet been stored, or
if the next byte to be transmitted is not yet ready. Some
microcontrollers, with limited hardware support for
ACCESS.bus, extend the access after each bit, thus allow-
ing the software to handle this bit.
Figure 5-13. Bit Transfer
5.7.2 Start and Stop Conditions
The ACCESS.bus master generates Start and Stop Condi-
tions (control codes). After a Start Condition is generated,
the bus is considered busy and retains this status for a cer-
tain time after a Stop Condition is generated. A high-to-low
transition of the data line (ABD) while the clock (ABC) is
high indicates a Start Condition. A low-to-high transition of
the ABD line while the ABC is high indicates a Stop Condi-
tion (Figure 5-14).
In addition to the first Start Condition, a repeated Start
Condition can be generated in the middle of a transaction.
This allows another device to be accessed, or a change in
the direction of data transfer.
Figure 5-14. Start and Stop Conditions
ABD
ABC
Data Line
Stable:
Data Valid Change
of Data
Allowed
ABD
ABC
S P
Start
Condition
Stop
Condition