Rainbow Electronics DS2152 - Manual (Page 9)

DS2152
031897 9/79
onto the T1 line. Can be internally connected to TNEGO
by tying the LIUC pin high. TPOSI and TNEGI can be
tied together in NRZ applications.
Transmit Clock Input [TCLKI]. Line interface transmit
clock. Can be internally connected to TCLKO by tying
the LIUC pin high.
RECEIVE SIDE DIGITAL PINS
Receive Link Data [RLINK]. Updated with either FDL
data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK
before the start of a frame. See Section 15 for details.
Receive Link Clock [RLCLK]. A 4 KHz or 2 KHz
(ZBTSI) clock for the RLINK output.
Receive Clock [RCLK]. 1.544 MHz clock that is used
to clock data through the receive side framer.
Receive Channel Clock [RCHCLK]. A 192 KHz clock
which pulses high during the LSB of each channel.
Synchronous with RCLK when the receive side elastic
store is disabled. Synchronous with RSYSCLK when
the receive side elastic store is enabled. Useful for par-
allel to serial conversion of channel data.
Receive Channel Block [RCHBLK]. A user program-
mable output that can be forced high or low during any of
the 24 T1 channels. Synchronous with RCLK when the
receive side elastic store is disabled. Synchronous with
RSYSCLK when the receive side elastic store is
enabled. Useful for blocking clocks to a serial UART or
LAPD controller in applications where not all T1 chan-
nels are used such as Fractional T1, 384K bps service,
768K bps, or ISDN–PRI. Also useful for locating individ-
ual channels in drop–and–insert applications, for exter-
nal per–channel loopback, and for per–channel condi-
tioning. See Section 9 for details.
Receive Serial Data [RSER]. Received NRZ serial
data. Updated on rising edges of RCLK when the
receive side elastic store is disabled. Updated on the
rising edges of RSYSCLK when the receive side elastic
store is enabled.
Receive Sync [RSYNC]. An extracted pulse, one
RCLK wide, is output at this pin which identifies either
frame (RCR2.4=0) or multiframe (RCR2.4=1) bound-
aries. If set to output frame boundaries then via
RCR2.5, RSYNC can also be set to output double–wide
pulses on signaling frames. If the receive side elastic
store is enabled via CCR1.2, then this pin can be
enabled to be an input via RCR2.3 at which a frame or
multiframe boundary pulse is applied. See Section 15
for details.
Receive Frame Sync [RFSYNC]. An extracted 8 KHz
pulse, one RCLK wide, is output at this pin which identi-
fies frame boundaries.
Receive Multiframe Sync [RMSYNC]. Only used
when the receive side elastic store is enabled. An
extracted pulse, one RSYSCLK wide, is output at this
pin which identifies multiframe boundaries. If the
receive side elastic store is disabled, then this output will
output multiframe boundaries associated with RCLK.
Receive Data [RDATA]. Updated on the rising edge of
RCLK with the data out of the receive side framer.
Receive System Clock [RSYSCLK]. 1.544 MHz or
2.048 MHz clock. Only used when the elastic store
function is enabled. Should be tied low in applications
that do not use the elastic store. Can be burst at rates up
to 8.192 MHz.
Receive Signaling Output [RSIG]. Outputs signaling
bits in a PCM format. Updated on rising edges of RCLK
when the receive side elastic store is disabled. Updated
on the rising edges of RSYSCLK when the receive side
elastic store is enabled.
Receive Loss of Sync / Loss of Transmit Clock
[RLOS/LOTC]. A dual function output that is controlled
by the CCR3.5 control bit. This pin can be programmed
to either toggle high when the synchronizer is searching
for the frame and multiframe or to toggle high if the TCLK
pin has not been toggled for 5 usec.
Receive Carrier Loss [RCL]. Set high when the line
interface detects a loss of carrier.
Receive Signaling Freeze [RSIGF]. Set high when the
signaling data is frozen via either automatic or manual
intervention. Used to alert downstream equipment of
the condition.
8 MHz Clock [8MCLK]. A 8.192 MHz output clock that
is referenced to the clock that is output at the RCLK pin