Rainbow Electronics DS2152 - Manual (Page 8)

DS2152
031897 8/79
DS2152 PIN DESCRIPTION Table 1–2
TRANSMIT SIDE DIGITAL PINS
Transmit Clock [TCLK]. A 1.544 MHz primary clock.
Used to clock data through the transmit side formatter.
Transmit Serial Data [TSER]. Transmit NRZ serial
data. Sampled on the falling edge of TCLK when the
transmit side elastic store is disabled. Sampled on the
falling edge of TSYSCLK when the transmit side elastic
store is enabled.
Transmit Channel Clock [TCHCLK]. A 192 KHz clock
which pulses high during the LSB of each channel. Syn-
chronous with TCLK when the transmit side elastic
store is disabled. Synchronous with TSYSCLK when
the transmit side elastic store is enabled. Useful for par-
allel to serial conversion of channel data.
Transmit Channel Block [TCHBLK]. A user program-
mable output that can be forced high or low during any of
the 24 T1 channels. Synchronous with TCLK when the
transmit side elastic store is disabled. Synchronous
with TSYSCLK when the transmit side elastic store is
enabled. Useful for blocking clocks to a serial UART or
LAPD controller in applications where not all T1 chan-
nels are used such as Fractional T1, 384 Kbps (H0),
768 Kbps or ISDN–PRI . Also useful for locating individ-
ual channels in drop–and–insert applications, for exter-
nal per–channel loopback, and for per–channel condi-
tioning. See Section 9 for details.
Transmit System Clock [TSYSCLK]. 1.544 MHz or
2.048 MHz clock. Only used when the transmit side
elastic store function is enabled. Should be tied low in
applications that do not use the transmit side elastic
store. Can be burst at rates up to 8.192 MHz.
Transmit Link Clock [TLCLK]. 4 KHz or 2 KHz
(ZBTSI) demand clock for the TLINK input. See Section
11 for details.Transmit Link Data [TLINK].
Transmit Link Data [TLINK]. If enabled via TCR1.2,
this pin will be sampled on the falling edge of TCLK for
data insertion into either the FDL stream (ESF) or the
Fs–bit position (D4) or the Z–bit position (ZBTSI). See
Section 11 for details.
Transmit Sync [TSYNC]. A pulse at this pin will estab-
lish either frame or multiframe boundaries for the trans-
mit side. Via TCR2.2, the DS2152 can be programmed
to output either a frame or multiframe pulse at this pin. If
this pin is set to output pulses at frame boundaries, it can
also be set via TCR2.4 to output double–wide pulses at
signaling frames. See Section 15 for details.
Transmit System Sync [TSSYNC]. Only used when
the transmit side elastic store is enabled. A pulse at this
pin will establish either frame or multiframe boundaries
for the transmit side. Should be tied low in applications
that do not use the transmit side elastic store.
Transmit Signaling Input [TSIG]. When enabled, this
input will sample signaling bits for reinsertion into outgo-
ing PCM T1 data stream. Sampled on the falling edge
of TCLK when the transmit side elastic store is disabled.
Sampled on the falling edge of TSYSCLK when the
transmit side elastic store is enabled.
Transmit Elastic Store Data Output [TESO].
Updated on the rising edge of TCLK with data out of the
the transmit side elastic store whether the elastic store
is enabled or not. This pin is normally tied to TDATA.
Transmit Data [TDATA]. Sampled on the falling edge
of TCLK with data to be clocked through the transmit
side formatter. This pin is normally tied to TESO.
Transmit Positive Data Output [TPOSO]. Updated on
the rising edge of TCLKO with the bipolar data out of the
transmit side formatter. Can be programmed to source
NRZ data via the Output Data Format (CCR1.6) control
bit. This pin is normally tied to TPOSI.
Transmit Negative Data Output [TNEGO]. Updated
on the rising edge of TCLKO with the bipolar data out of
the transmit side formatter. This pin is normally tied to
TNEGI.
Transmit Clock Output [TCLKO]. Buffered clock that
is used to clock data through the transmit side formatter
(i.e., either TCLK or RCLKI). This pin is normally tied to
TCLKI.
Transmit Positive Data Input [TPOSI]. Sampled on
the falling edge of TCLKI for data to be transmitted out
onto the T1 line. Can be internally connected to TPOSO
by tying the LIUC pin high. TPOSI and TNEGI can be
tied together in NRZ applications.
Transmit Negative Data Input [TNEGI]. Sampled on
the falling edge of TCLKI for data to be transmitted out