Rainbow Electronics DS2152 - Manual (Page 46)

DS2152
031897 46/79
11.1.4 HDLC/BOC Register Description
FDLC: FDL CONTROL REGISTER (Address=00 Hex)
(MSB) (LSB)
RBR RHR TFS THR TABT TEOM TZSD TCRCD
SYMBOL POSITION NAME AND DESCRIPTION
RBR FDLC.7 Receive BOC Reset. A 0 to 1 transition will reset the BOC circuitry. Must
be cleared and set again for a subsequent reset.
RHR FDLC.6 Receive HDLC Reset. A 0 to 1 transition will reset the HDLC controller.
Must be cleared and set again for a subsequent reset.
TFS FDLC.5 Transmit Flag/Idle Select.
0 = 7Eh
1 = FFh
THR FDLC.4 Transmit HDLC Reset. A 0 to 1 transition will reset both the HDLC control-
ler and the transmit BOC circuitry. Must be cleared and set again for a sub-
sequent reset.
TABT FDLC.3 Transmit Abort. A 0 to 1 transition will cause the FIFO contents to be
dumped and one FEh abort to be sent followed by 7Eh or FFh flags/idle until
a new packet is initiated by writing new data into the FIFO. Must be cleared
and set again for a subsequent abort to be sent.
TEOM FDLC.2 Transmit End of Message. Should be set to a one just before the last data
byte of a HDLC packet is written into the transmit FIFO at TFFR. This bit will
be cleared by the HDLC controller when the last byte has been transmitted.
TZSD FDLC.1 Transmit Zero Stuffer Defeat. Overrides internal enable.
0 = enable the zero stuffer (normal operation)
1 = disable the zero stuffer
TCRCD FDLC.0 Transmit CRC Defeat.
0 = enable CRC generation (normal operation)
1 = disable CRC generation
FDLS: FDL STATUS REGISTER (Address=01 Hex)
(MSB) (LSB)
RBOC RPE RPS RHALF RNE THALF TNF TMEND
SYMBOL POSITION NAME AND DESCRIPTION
RBOC FDLS.7 Receive BOC Detector Change of State. Set whenever the BOC detec-
tor sees a change of state from a BOC Detected to a No Valid Code seen or
vice versa. The setting of this bit prompt the user to read the RBOC register
for details.
RPE FDLS.6 Receive Packet End. Set when the HDLC controller detects either the fin-
ish of a valid message (i.e., CRC check complete) or when the controller
has experienced a message fault such as a CRC checking error, or an
overrun condition, or an abort has been seen. The setting of this bit
prompts the user to read the RPRM register for details.