Rainbow Electronics DS2152 - Manual (Page 20)

DS2152
031897 20/79
ODF CCR1.6 Output Data Format.
0 = bipolar data at TPOSO and TNEGO
1 = NRZ data at TPOSO; TNEGO = 0
RSAO CCR1.5 Receive Signaling All One’s. This bit should not be enabled if hardware
signaling is being utilized. See Section 7 for more details.
0 = allow robbed signaling bits to appear at RSER
1 = force all robbed signaling bits at RSER to one
TSCLKM CCR1.4 TSYSCLK Mode Select.
0 = if TSYSCLK is 1.544 MHz
1 = if TSYSCLK is 2.048 MHz
RSCLKM CCR1.3 RSYSCLK Mode Select.
0 = if RSYSCLK is 1.544 MHz
1 = if RSYSCLK is 2.048 MHz
RESE CCR1.2 Receive Elastic Store Enable.
0 = elastic store is bypassed
1 = elastic store is enabled
PLB CCR1.1 Payload Loopback.
0 = loopback disabled
1 = loopback enabled
FLB CCR1.0 Framer Loopback.
0 = loopback disabled
1 = loopback enabled
Payload Loopback
When CCR1.1 is set to a one, the DS2152 will be forced
into Payload LoopBack (PLB). Normally, this loopback
is only enabled when ESF framing is being performed
but can be enabled also in D4 framing applications. In a
PLB situation, the DS2152 will loop the 192 bits of pay-
load data (with BPVs corrected) from the receive sec-
tion back to the transmit section. The FPS framing pat-
tern, CRC6 calculation, and the FDL bits are not looped
back, they are reinserted by the DS2152. When PLB is
enabled, the following will occur:
1. data will be transmitted from the TPOSO and
TNEGO pins synchronous with RCLK instead of
TCLK
2. all of the receive side signals will continue to oper-
ate normally
3. the TCHCLK and TCHBLK signals are forced low
4. data at the TSER, TDATA, and TSIG pins is
ignored
5. the TLCLK signal will become synchronous with
RCLK instead of TCLK.
Framer Loopback
When CCR1.0 is set to a one, the DS2152 will enter a
Framer LoopBack (FLB) mode. This loopback is useful
in testing and debugging applications. In FLB, the
DS2152 will loop data from the transmit side back to the
receive side. When FLB is enabled, the following will
occur:
1. an unframed all one’s code will be transmitted at
TPOSO and TNEGO
2. data at RPOSI and RNEGI will be ignored
3. all receive side signals will take on timing synchro-
nous with TCLK instead of RCLKI.
Please note that it is not acceptable to have RCLK tied
to TCLK during this loopback because this will cause an
unstable condition.