Rainbow Electronics DS2152 - Manual (Page 24)

DS2152
031897 24/79
TCM4 CCR5.4 Transmit Channel Monitor Bit 4. MSB of a channel decode that deter-
mines which transmit channel data will appear in the TDS0M register. See
Section 6 for details.
TCM3 CCR5.3 Transmit Channel Monitor Bit 3.
TCM2 CCR5.2 Transmit Channel Monitor Bit 2.
TCM1 CCR5.1 Transmit Channel Monitor Bit 1.
TCM0 CCR5.0 Transmit Channel Monitor Bit 0. LSB of the channel decode.
Local Loopback
When CCR5.6 is set to a one, the DS2152 will be forced
into Local LoopBack (LLB). In this loopback, data will
continue to be transmitted as normal through the trans-
mit side of the DS2152 (unless LIAIS = 1). Data being
received at RTIP and RRING will be replaced with the
data being transmitted. Data in this loopback will pass
through the jitter attenuator. Please see Figure 1–1 for
more details. Please note that it is not acceptable to
have RCLKO tied to TCLKI during this loopback
because this will cause an unstable condition. Also it is
recommended that the jitter attenuator be placed on the
transmit side during this loopback.
CCR6: COMMON CONTROL REGISTER 6 (Address=1E Hex)
(MSB) (LSB)
RJC – – RCM4 RCM3 RCM2 RCM1 RCM0
SYMBOL POSITION NAME AND DESCRIPTION
RJC CCR6.7 Receive Japanese CRC6 Enable.
0 = use ANSI/AT&T/ITU CRC6 calculation (normal operation)
1 = use Japanese standard JT–G704 CRC6 calculation
– CCR6.6 Not Assigned. Should be set to zero when written.
– CCR6.5 Not Assigned. Should be set to zero when written.
RCM4 CCR6.4 Receive Channel Monitor Bit 4. MSB of a channel decode that deter-
mines which receive channel data will appear in the RDS0M register. See
Section 6 for details.
RCM3 CCR6.3 Receive Channel Monitor Bit 3.
RCM2 CCR6.2 Receive Channel Monitor Bit 2.
RCM1 CCR6.1 Receive Channel Monitor Bit 1.
RCM0 CCR6.0 Receive Channel Monitor Bit 0. LSB of the channel decode.
CCR7: COMMON CONTROL REGISTER 7 (Address=0A Hex)
(MSB) (LSB)
LIRST RLB – – – – – –
SYMBOL POSITION NAME AND DESCRIPTION
LIRST CCR7.7 Line Interface reset. Setting this bit from a zero to a one will initiate an
internal reset that affects the clock recovery state machine and jitter attenu-
ator. Normally this bit is only toggled on power–up. Must be cleared and set
again for a subsequent reset.