Rainbow Electronics DS2152 - Manual (Page 39)

DS2152
031897 39/79
Each of the bit position in the Transmit Idle Registers
(TIR1/TIR2/TIR3) represent a DS0 channel in the out-
going frame. When these bits are set to a one, the corre-
sponding channel will transmit the Idle Code contained
in the Transmit Idle Definition Register (TIDR). Robbed
bit signaling and Bit 7 stuffing will occur over the pro-
grammed Idle Code unless the DS0 channel is made
transparent by the Transmit Transparency Registers.
The Transmit Idle Registers (TIRs) have an alternate
function that allow them to define a Per–Channel Loop-
Back (PCLB). If the TIRFS control bit (CCR4.0) is set to
one, then the TIRs will determine which channels (if
any) from the backplane should be replaced with the
data from the receive side or in other words, off of the T1
line. If this mode is enabled, then transmit and receive
clocks and frame syncs must be synchronized. One
method to accomplish this would be to tie RCLK to
TCLK and RFSYNC to TSYNC.
TIR1/TIR2/TIR3: TRANSMIT IDLE REGISTERS (Address=3C to 3E Hex)
[Also used for Per–Channel Loopback]
(MSB) (LSB)
CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
SYMBOL POSITION NAME AND DESCRIPTION
CH24 TIR3.7 Transmit Idle Registers.
0=do not insert the Idle Code in the TIDR into this channel
CH1 TIR1.0 1 = insert the Idle Code in the TIDR into this channel
NOTE:
If CCR4.0=1, then a zero in the TIRs implies that channel data is to be sourced from TSER and a one implies that
channel data is to be sourced from the output of the receive side framer (i.e., Per–Channel Loopback; see Figure 1–1).
TIDR: TRANSMIT IDLE DEFINITION REGISTER (Address=3F Hex)
(MSB) (LSB)
TIDR7 TIDR6 TIDR5 TIDR4 TIDR3 TIDR2 TIDR1 TIDR0
SYMBOL POSITION NAME AND DESCRIPTION
TIDR7 TIDR.7 MSB of the Idle Code (this bit is transmitted first)
TIDR0 TIDR.0 LSB of the Idle Code (this bit is transmitted last)
8.1.2 Per–Channel Code Insertion
The second method involves using the Transmit Chan-
nel Control Registers (TCC1/2/3) to determine which of
the 24 T1 channels should be overwritten with the code
placed in the Transmit Channel Registers (TC1 to
TC24). This method is more flexible than the first in that
it allows a different 8–bit code to be placed into each of
the 24 T1 channels.
TIR1 (3C)
TIR2 (3D)
TIR3 (3E)