Rainbow Electronics DS2152 - Manual (Page 43)

DS2152
031897 43/79
10.1 RECEIVE SIDE
If the receive side elastic store is enabled (CCR1.2=1),
then the user must provide either a 1.544 MHz
(CCR1.3=0) or 2.048 MHz (CCR1.3=1) clock at the
RSYSCLK pin. The the user has the option of either pro-
viding a frame/multiframe sync at the RSYNC pin
(RCR2.3=1) or having the RSYNC pin provide a pulse
on frame boundaries (RCR2.3=0). If the user wishes to
obtain pulses at the frame boundary, then RCR2.4 must
be set to zero and if the user wishes to have pulses
occur at the multiframe boundary, then RCR2.4 must be
set to one. The DS2152 will always indicate frame
boundaries via the RFSYNC output whether the elastic
store is enabled or not. If the elastic store is enabled,
then multiframe boundaries will be indicated via the
RMSYNC ouput. If the user selects to apply a
2.048 MHz clock to the RSYSCLK pin, then the data out-
put at RSER will be forced to all ones every fourth chan-
nel and the F–bit will be deleted. Hence channels 1, 5, 9,
13, 17, 21, 25, and 29 (timeslots 0, 4, 8, 12, 16, 20, 24,
and 28) will be forced to a one. Also, in 2.048 MHz
applications, the RCHBLK output will be forced high
during the same channels as the RSER pin. See Sec-
tion 15 for more details. This is useful in T1 to CEPT (E1)
conversion applications. If the 386–bit elastic buffer
either fills or empties, a controlled slip will occur. If the
buffer empties, then a full frame of data (193 bits) will be
repeated at RSER and the SR1.4 and RIR1.3 bits will be
set to a one. If the buffer fills, then a full frame of data will
be deleted and the SR1.4 and RIR1.4 bits will be set to a
one.
10.2 TRANSMIT SIDE
The operation of the transmit elastic store is very similar
to the receive side. The transmit side elastic store is
enabled via CCR1.7. A 1.544 MHz (CCR1.4=0) or
2.048 MHz (CCR1.4=1) clock can be applied to the
TSYSCLK input. If the user selects to apply a
2.048 MHz clock to the TSYSCLK pin, then the data
input at TSER will be ignored every fourth channel.
Hence channels 1, 5, 9, 13, 17, 21, 25, and 29 (timeslots
0, 4, 8, 12, 16, 20, 24, and 28) will be ignored. The user
must supply a 8 KHz frame sync pulse to the TSSYNC
input. Also, in 2.048 MHz applications, the TCHBLK
output will be forced high during the channels ignored by
the DS2152. See Section 15 for more details. Con-
trolled slips in the transmit elastic store are reported in
the RIR2.3 bit and the direction of the slip is reported in
the RIR2.5 and RIR2.4 bits.
10.3 MINIMUM DELAY SYNCHRONOUS
RSYSCLK/TSYSCLK MODE
In applications where the DS2152 is connected to back-
planes that are frequency locked to the recovered T1
clock (i.e., the RCLK output), the full two frame depth of
the onboard elastic stores is really not needed. In fact,
in some delay sensitive applications, the normal two
frame depth may be excessive. If the CCR3.7 bit is set
to one, then the receive elastic store (and also the trans-
mit elastic store if it is enabled) will be forced to a maxi-
mum depth of 32 bits instead of the normal 386 bits. In
this mode, RSYSCLK and TSYSCLK must be tied
together and they must be frequency locked to RCLK.
All of the slip contention logic in the DS2152 is disabled
(since slips cannot occur). Also, since the buffer depth
is no longer two frames deep, the DS2152 must be set
up to source a frame pulse at the RSYNC pin and this
output must be tied to the TSSYNC input. On power–up
after the RSYSCLK and TSYSCLK signals have locked
to the RCLK signal, the elastic store reset bit (CCR3.6)
should be toggled from a zero to a one to insure proper
operation.
11.0 FDL/Fs EXTRACTION AND INSERTION
The DS2152 has the ability to extract/insert data from/
into the Facility Data Link (FDL) in the ESF framing
mode and from/into Fs–bit position in the D4 framing
mode. Since SLC–96 utilizes the Fs–bit position, this
capability can also be used in SLC–96 applications.
The DS2152 contains a complete HDLC and BOC con-
troller for the FDL and this operation is covered in Sec-
tion 11.1. To allow for backward compatibility between
the DS2152 and earlier devices, the DS2152 maintains
some legacy functionality for the FDL and this is cov-
ered in Section 11.2. Section 11.3 covers D4 and
SLC–96 operation. Please contact the factory for a
copy of C language source code for implementing the
FDL on the DS2152.
11.1 HDLC AND BOC CONTROLLER FOR
THE FDL
11.1.1 General Overview
The DS2152 contains a complete HDLC controller with
16–byte buffers in both the transmit and receive direc-
tions as well as separate dedicated hardware for Bit Ori-
ented Codes (BOC). The HDLC controller performs all
the necessary overhead for generating and receiving