Rainbow Electronics DS2152 - Manual (Page 55)

DS2152
031897 55/79
C4 RDNCD.4 Receive Down Code Definition Bit 4. A Don’t Care if a 1 to 3 bit length is
selected.
C3 RDNCD.3 Receive Down Code Definition Bit 3. A Don’t Care if a 1 to 4 bit length is
selected.
C2 RDNCD.2 Receive Down Code Definition Bit 2. A Don’t Care if a 1 to 5 bit length is
selected.
C1 RDNCD.1 Receive Down Code Definition Bit 1. A Don’t Care if a 1 to 6 bit length is
selected.
C0 RDNCD.0 Receive Down Code Definition Bit 0. A Don’t Care if a 1 to 7 bit length is
selected.
13.0 TRANSMIT TRANSPARENCY
Each of the 24 T1 channels in the transmit direction of
the DS2152 can be either forced to be transparent or in
other words, can be forced to stop Bit 7 Stuffing and/or
Robbed Signaling from overwriting the data in the chan-
nels. Transparency can be invoked on a channel by
channel basis by properly setting the TTR1, TTR2, and
TTR3 registers.
TTR1/TTR2/TTR3: TRANSMIT TRANSPARENCY REGISTER (Address=39 to 3B Hex)
(MSB) (LSB)
CH8 CH7 CH6 CH5 CH4 CH3 CH2 CH1
CH16 CH15 CH14 CH13 CH12 CH11 CH10 CH9
CH24 CH23 CH22 CH21 CH20 CH19 CH18 CH17
SYMBOL POSITION NAME AND DESCRIPTION
CH24 TTR3.7 Transmit Transparency Registers.
0=this DS0 channel is not transparent
CH1 TTR1.0 1=this DS0 channel is transparent
Each of the bit position in the Transmit Transparency
Registers (TTR1/TTR2/TTR3) represent a DS0 chan-
nel in the outgoing frame. When these bits are set to a
one, the corresponding channel is transparent (or
clear). If a DS0 is programmed to be clear, no robbed bit
signaling will be inserted nor will the channel have Bit 7
stuffing performed. However, in the D4 framing mode,
bit 2 will be overwritten by a zero when a Yellow Alarm is
transmitted. Also the user has the option to prevent the
TTR registers from determining which channels are to
have Bit 7 stuffing performed. If the TCR2.0 and
TCR1.3 bits are set to one, then all 24 T1 channels will
have Bit 7 stuffing performed on them regardless of how the TTR registers are programmed. In this manner, the
TTR registers are only affecting which channels are to
have robbed bit signaling inserted into them. Please
see Figure 15–11 for more details.
14.0 LINE INTERFACE FUNCTION
The line interface function in the DS2152 contains three
sections; (1) the receiver which handles clock and data
recovery, (2) the transmitter which waveshapes and
drives the T1 line, and (3) the jitter attenuator. Each of
the these three sections is controlled by the Line Inter-
face Control Register (LICR) which is described below.
TTR1 (39)
TTR2 (3A)
TTR3 (3B)