Rainbow Electronics DS2152 - Manual (Page 75)

DS2152
031897 75/79
TRANSMIT SIDE AC TIMING Figure 16–7
t R t F
t CP
t CL t CH
t SU
t D2
t HD
t D2
t D2
t D2
t PW
t SU
t HD
t SU
TCLK
TSER/TSIG/
TDATA
TCHCLK
TCHBLK
TSYNC 1
TSYNC 2
TLCLK 5
TLINK
t D1
TESO
NOTES:
1. TSYNC is in the output mode (TCR2.2=1).
2. TSYNC is in the input mode (TCR2.2=0).
3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled.
4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled.
5. TLINK is only sampled during F–bit locations.
6. No relationship between TCHCLK and TCHBLK and the other signals is implied.