Rainbow Electronics DS2152 - Manual (Page 31)

DS2152
031897 31/79
RFDL IMR2.4 Receive FDL Buffer Full.
0 = interrupt masked
1 = interrupt enabled
TFDL IMR2.3 Transmit FDL Buffer Empty.
0 = interrupt masked
1 = interrupt enabled
RMTCH IMR2.2 Receive FDL Match Occurrence.
0 = interrupt masked
1 = interrupt enabled
RAF IMR2.1 Receive FDL Abort.
0 = interrupt masked
1 = interrupt enabled
RSC IMR2.0 Receive Signaling Change.
0 = interrupt masked
1 = interrupt enabled
5.0 ERROR COUNT REGISTERS
There are a set of three counters in the DS2152 that
record bipolar violations, excessive zeros, errors in the
CRC6 code words, framing bit errors, and number of
multiframes that the device is out of receive synchro-
nization. Each of these three counters are automatically
updated on either one second boundaries (CCR3.2=0)
or every 42 ms (CCR3.2=1) as determined by the timer
in Status Register 2 (SR2.5). Hence, these registers
contain performance data from either the previous
second or the previous 42 ms. The user can use the
interrupt from the one second timer to determine when
to read these registers. The user has a full second (or
42 ms) to read the counters before the data is lost. All
three counters will saturate at their respective maximum
counts and they will not rollover (note: only the Line
Code Violation Count Register has the potential to over-
flow but the bit error would have to exceed 10 –2 before
this would occur).
5.1 Line Code Violation Count Register
(LCVCR)
Line Code Violation Count Register 1 High (LCVCR1) is
the most significant word and LCVCR2 is the least sig-
nificant word of a 16–bit counter that records code viola-
tions (CVs). CVs are defined as Bipolar Violations
(BPVs) or excessive zeros. See Table 5.1 for details of
exactly what the LCVCRs count. If the B8ZS mode is
set for the receive side via CCR2.2, then B8ZS code
words are not counted. This counter is always enabled;
it is not disabled during receive loss of synchronization
(RLOS=1) conditions.
LCVCR1: LINE CODE VIOLATION COUNT REGISTER 1 (Address = 23 Hex)
LCVCR2: LINE CODE VIOLATION COUNT REGISTER 2 (Address = 24 Hex)
(MSB) (LSB)
LCV15 LCV14 LCV13 LCV12 LCV11 LCV10 LCV9 LCV8
LCV7 LCV6 LCV5 LCV4 LCV3 LCV2 LCV1 LCV0
SYMBOL POSITION NAME AND DESCRIPTION
LCV15 LCVCR1.7 MSB of the 16–bit code violation count
LCV0 LCVCR2.0 LSB of the 10–bit code violation count
LCVCR1
LCVCR2