Rainbow Electronics DS2152 - Manual (Page 26)

DS2152
031897 26/79
4.0 STATUS AND INFORMATION
REGISTERS
There is a set of nine registers that contain information
on the current real time status of the DS2152, Status
Register 1 (SR1), Status Register 2 (SR2), Receive
Information Registers 1 to 3 (RIR1/RIR2/RIR3) and a
set of four registers for the onboard HDLC and BOC
controller for the FDL. The specific details on the four
registers pertaining to the FDL are covered in
Section 11.1 but they operate the same as the other sta-
tus registers in the DS2152 and this operation is
described below.
When a particular event has occurred (or is occuring),
the appropriate bit in one of these nine registers will be
set to a one. All of the bits in SR1, SR2, RIR1, RIR2, and
RIR3 registers operate in a latched fashion. This means
that if an event or an alarm occurs and a bit is set to a one
in any of the registers, it will remain set until the user
reads that bit. The bit will be cleared when it is read and
it will not be set again until the event has occurred again
(or in the case of the RBL, RYEL, LRCL, and RLOS
alarms, the bit will remain set if the alarm is still present).
There are bits in the four FDL status registers that are
not latched and these bits are listed in Section 11.1.
The user will always proceed a read of any of the nine
registers with a write. The byte written to the register will
inform the DS2152 which bits the user wishes to read
and have cleared. The user will write a byte to one of
these registers, with a one in the bit positions he or she
wishes to read and a zero in the bit positions he or she
does not wish to obtain the latest information on. When
a one is written to a bit location, the read register will be
updated with the latest information. When a zero is writ-
ten to a bit position, the read register will not be updated
and the previous value will be held. A write to the status
and information registers will be immediately followed
by a read of the same register. The read result should be
logically AND’ed with the mask byte that was just written
and this value should be written back into the same reg-
ister to insure that bit does indeed clear. This second
write step is necessary because the alarms and events
in the status registers occur asynchronously in respect
to their access via the parallel port. This write–read–
write scheme allows an external microcontroller or
microprocessor to individually poll certain bits without
disturbing the other bits in the register. This operation is
key in controlling the DS2152 with higher–order soft-
ware languages.
The SR1, SR2, and FDLS registers have the unique
ability to initiate a hardware interrupt via the INT output
pin. Each of the alarms and events in the SR1, SR2, and
FDLS can be either masked or unmasked from the inter-
rupt pin via the Interrupt Mask Register 1 (IMR1), Inter-
rupt Mask Register 2 (IMR2), and FDL Interrupt Mask
Register (FIMR) respectively. The FIMR register is cov-
ered in Section 11.1.
The interrupts caused by alarms in SR1 (namely RYEL,
LRCL, RBL, and RLOS) act differently than the inter-
rupts caused by events in SR1 and SR2 (namely LUP,
LDN, LOTC, RSLIP, RMF, TMF, SEC, RFDL, TFDL,
RMTCH, RAF, and RSC) and FIMR. The alarm caused
interrupts will force the INT pin low whenever the alarm
changes state (i.e., the alarm goes active or inactive
according to the set/clear criteria in Table 4–2). The INT
pin will be allowed to return high (if no other interrupts
are present) when the user reads the alarm bit that
caused the interrupt to occur even if the alarm is still
present.
The event caused interrupts will force the INT pin low
when the event occurs. The INT pin will be allowed to
return high (if no other interrupts are present) when the
user reads the event bit that caused the interrupt to
occur.
RIR1: RECEIVE INFORMATION REGISTER 1 (Address=22 Hex)
(MSB) (LSB)
COFA 8ZD 16ZD RESF RESE SEFE B8ZS FBE
SYMBOL POSITION NAME AND DESCRIPTION
COFA RIR1.7 Change of Frame Alignment. Set when the last resync resulted in a
change of frame or multiframe alignment.
8ZD RIR1.6 Eight Zero Detect. Set when a string of at least eight consecutive zeros
(regardless of the length of the string) have been received at RPOSI and
RNEGI.