Renesas 4514 - Manual (Page 97)

1-84
HARDWARE
4513/4514 Group User’s Manual
V1 3
V1 2
V1 1
V1 0
V2 3
V2 2
V2 1
V2 0
Serial I/O interrupt enable bit
A-D interrupt enable bit
Timer 4 interrupt enable bit
Timer 3 interrupt enable bit
Interrupt control register V1
Timer 2 interrupt enable bit
Timer 1 interrupt enable bit
External 1 interrupt enable bit
External 0 interrupt enable bit
Interrupt disabled (SNZT2 instruction is valid)
Interrupt enabled (SNZT2 instruction is invalid)
Interrupt disabled (SNZT1 instruction is valid)
Interrupt enabled (SNZT1 instruction is invalid)
Interrupt disabled (SNZ1 instruction is valid)
Interrupt enabled (SNZ1 instruction is invalid)
Interrupt disabled (SNZ0 instruction is valid)
Interrupt enabled (SNZ0 instruction is invalid)
Interrupt disabled (SNZSI instruction is valid)
Interrupt enabled (SNZSI instruction is invalid)
Interrupt disabled (SNZAD instruction is valid)
Interrupt enabled (SNZAD instruction is invalid)
Interrupt disabled (SNZT4 instruction is valid)
Interrupt enabled (SNZT4 instruction is invalid)
Interrupt disabled (SNZT3 instruction is valid)
Interrupt enabled (SNZT3 instruction is invalid)
0
1
0
1
0
1
0
1
R/W at RAM back-up : 0000 2 at reset : 0000 2 R/W at RAM back-up : 0000 2 at reset : 0000 2
Interrupt control register V2 R/W at RAM back-up : 0000 2 at reset : 0000 2
0
1
0
1
0
1
0
1
CONTROL REGISTERS
I1 3
I1 2
I1 1
I1 0
I2 3
I2 2
I2 1
I2 0
Not used
Interrupt valid waveform for INT0 pin/
return level selection bit (Note 2)
INT0 pin edge detection circuit control bit
INT0 pin
timer 1 control enable bit
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT1 pin is recognized with the SNZI1
instruction)/“L” level
Rising waveform (“H” level of INT1 pin is recognized with the SNZI1
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
Enabled
Not used
Interrupt valid waveform for INT1 pin/
return level selection bit (Note 3)
INT1 pin edge detection circuit control bit
INT1 pin
timer 3 control enable bit
Notes 1: “R” represents read enabled, and “W” represents write enabled.
2: When the contents of I1 2 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction.
3: When the contents of I2 2 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction.
Interrupt control register I1 R/W at RAM back-up : state retained at reset : 0000 2
This bit has no function, but read/write is enabled.
Falling waveform (“L” level of INT0 pin is recognized with the SNZI0
instruction)/“L” level
Rising waveform (“H” level of INT0 pin is recognized with the SNZI0
instruction)/“H” level
One-sided edge detected
Both edges detected
Disabled
Enabled
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Interrupt control register I2 R/W at RAM back-up : state retained at reset : 0000 2
CONTROL REGISTERS