Renesas 4514 - Manual (Page 34)

4513/4514 Group User’s Manual
HARDWARE
1-21
FUNCTION BLOCK OPERATIONS
DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with
the SB j, RB j, and SZB j instructions) is enabled for the entire
memory area. A RAM address is specified by a data pointer. The
data pointer consists of registers Z, X, and Y. Set a value to the
data pointer certainly when executing an instruction to access
RAM.
Table 2 shows the RAM size. Figure 12 shows the RAM map.
Fig. 12 RAM map
Table 2 RAM size
Product
M34513M2
M34513M4/E4
M34513M6
M34513M8/E8
M34514M6
M34514M8/E8
RAM size
128 words ✕ 4 bits (512 bits)
256 words ✕ 4 bits (1024 bits)
384 words ✕ 4 bits (1536 bits)
384 words ✕ 4 bits (1536 bits)
384 words ✕ 4 bits (1536 bits)
384 words ✕ 4 bits (1536 bits)
M34513M6
M34513M8/E8
M34514M6
M34514M8/E8
M34513M4/E4
M34513M2
Z=0, X=0 to 15
Z=0, X=0 to 7
Z=0, X=0 to 15
Z=1, X=0 to 7
Register Y
Register Z
Register X
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0 1 7
1
RAM 384 words ✕ 4 bits (1536 bits)
2 3 6 0 15
384 words
256 words
128 words
4 5 1 7 2 3 6 4 5