Mpu parity error, Mpu offboard error, Mpu tea - cause unidentified – Motorola MVME1X7P User Manual
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Programming Issues
1
MPU Parity Error
MPU Offboard Error
MPU TEA - Cause Unidentified
Description:
A DRAM parity error.
MPU Notification:
TEA is asserted during an MPU DRAM access.
Status:
Bit 9 of the MPU Status and DMA Interrupt Count register
in the VMEchip2 at address $FFF40048.
Comments:
After memory has been initialized, this error normally
indicates a hardware problem.
Description:
An error occurred while the MPU was attempting to access
an offboard resource.
MPU Notification:
TEA is asserted during offboard access.
Status:
Bit 8 of the MPU Status and DMA Interrupt Count
register.
Address $FFF40048
Comments:
This can be caused by a VMEbus timeout, a VMEbus
BERR
∗
, or a single-board computer VMEbus access
timeout. The latter is the time from when the VMEbus has
been requested to when it is granted.
Description:
An error occurred while the MPU was attempting an
access.
MPU Notification:
TEA is asserted during an MPU access.
Status:
Bit 10 of the MPU Status and DMA Interrupt Count
register.
Address $FFF40048
Comments:
No status was given as to the cause of the TEA assertion.