Motorola MVME1X7P User Manual
Page 305

IN-3
I
N
D
E
X
clear-on-compare mode, VMEchip2 counters
clocks for VMEchip2 counters and timers
command chaining mode, VMEchip2
command packets, DMAC
compatibility, backward
connection diagrams
printer and serial port
transition module
Control and Status registers (CSRs),
memory map
counter enable
D
data access cycles, VMEbus
data bus structure
data sheets, sources of
data transfer capabilities
local-bus-to-VMEbus interface
VMEbus-to-local-bus interface
data transfer size, VMEchip2 DMAC
data transfers, DMA (VMEchip2 ASIC)
data transfers, VMEbus
DCE connections (serial ports)
debugging packages
decimal number, symbol for
decoders
devices, normal address range
DFAIR bit
differences from previous boards
direct mode
DMA
transfers, no-address-increment
DMA Controller (DMAC), VMEchip2 ASIC
DMAC
command packets
parity error
TEA, cause unidentified
VMEbus requester
DMAC registers (VMEchip2 ASIC)
DMAC byte counter
DMAC Control register 1 (bits 0-7)
DMAC Control register 2 (bits 0-7)
DMAC Control register 2 (bits 8-15)
DMAC local bus address counter
DMAC Status register
DMAC VMEbus address counter
Local-Bus-to-VMEbus Requester
Control register
MPU Status and DMA Interrupt Count
register
PROM Decoder, SRAM and DMA
Control register
table address counter
VMEbus Interrupter Control register
VMEbus Interrupter Vector register
double bit error
DRAM
map decoder
specifications
DS1210S device
DTACK* signal (VMEchip2 ASIC)
DTE connections (serial ports)
dump, performing
DWB bit (VMEchip2 LCSR)