Motorola MVME1X7P - Manual (Page 145)

LCSR Programming Model
http://www.motorola.com/computer/literature 2-55
2
0 The request level is 0.
1 The request level is 1.
2 The request level is 2.
3 The request level is 3.
LVRWD When this bit is high, the requester operates in
release-when-done mode. When this bit is low, the
requester operates in release-on-request mode.
LVFAIR When this bit is high, the requester operates in fair mode.
When this bit is low, the requester does not operate in fair
mode. In fair mode, the requester waits until the request
signal line for the selected level is inactive before
requesting the VMEbus.
DWB When this bit is high, the VMEchip2 requests the
VMEbus and does not release it. When this bit is low, the
VMEchip2 releases the VMEbus according to the release
mode programmed in the LVRWD bit. When the
VMEbus has been acquired, the DHB bit is set.
DHB When this bit is high, the VMEbus has been acquired in
response to the DWB bit being set. When the DWB bit is
cleared, this bit is cleared.
ROBN When this bit is high, the VMEbus arbiter operates in
round-robin mode. When this bit is low, the arbiter
operates in priority mode.
DMAC Control Register 1 (bits 0-7)
This control register is loaded by the processor; it is not modified when the
DMAC loads new values from the command packet.
DREQL These bits define the VMEbus request level for the
DMAC requester. The request level can only change
while the VMEchip2 is bus master. The VMEchip2
ADR/SIZ $FFF40030 (8 bits of 32)
BIT 7 6 5 4 3 2 1 0
NAME DHALT DEN DTBL DFAIR DRELM DREQL
OPER S S R/W R/W R/W R/W
RESET 0 PS 0 PS 0 PS 0 PS 0 PS 0 PS