82596ca lanc interrupt control register, 82596ca lanc interrupt control register -35 – Motorola MVME1X7P User Manual
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3-35
3
82596CA LANC Interrupt Control Register
IL2-IL0
Interrupt Request Level. These three bits select the
interrupt level for the 82596CA LANC. Level 0 does not
generate an interrupt.
ICLR
In edge-sensitive mode, writing a logic 1 to this bit clears
the INT status bit. This bit has no function in level-
sensitive mode. This bit is always read as zero.
IEN
Interrupt Enable. When this bit is high, the interrupt is
enabled. The interrupt is disabled when this bit is low.
INT
This status bit reflects the state of the INT pin from the
LANC (qualified by the IEN bit). When this bit is high, a
LANC INT interrupt is being generated at the level
programmed in IL2-IL0 (if nonzero).
E/L*
Edge or Level. When this bit is high, the interrupt is edge-
sensitive. The interrupt is level-sensitive when this bit is
low.
PLTY
Polarity.
When this bit is low, interrupt is activated by a rising
edge/high level of the LANC INT pin.
When this bit is high, interrupt is activated by a falling
edge/low level of the LANC INT pin.
Note that if this bit is changed while the E/L* bit is set (or
is being set), a LANC interrupt may be generated. This
can be avoided by setting the ICLR bit during write cycles
that change the E/L* bit.
ADR/SIZ
$FFF4202A (8 bits)
BIT
15
14
13
12
11
10
9
8
NAME
PLTY
E/L*
INT
IEN
ICLR
IL2
IL1
IL0
OPER
R/W
R/W
R
R/W
C
R/W
R/W
R/W
RESET
0 PL
0 PL
0 PL
0 PL
0 PL
0 PL
0 PL
0 PL